Abstract
Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.
Highlights
Thanks to its very low switching noise capability and to its intrinsic robustness, MOS current mode logic (MCML) is still a very popular digital circuit approach which finds use in a wide range of applications, from high-accuracy mixed-signal circuits to very highspeed integrated systems [1,2,3,4,5,6,7,8,9,10,11,12]
Considering the frequency divider architecture based on the cascade of nType DIV2 blocks with a level shifter at the clock input discussed in [34], the inspection of the results reported for a divide-by-eight frequency divider shows that only the cases with customized DIV2 blocks according to (16) seem of interest, since the others, despite the simpler design procedure, have apparently a non-negligible price in terms of power consumption
We report the simulation results of the frequency dividers by 16 based on the folded MCML (FMCML) latches exploiting forward body bias (FBB), designed according to the different approaches and design guidelines described in the previous sections
Summary
Thanks to its very low switching noise capability and to its intrinsic robustness, MOS current mode logic (MCML) is still a very popular digital circuit approach which finds use in a wide range of applications, from high-accuracy mixed-signal circuits to very highspeed integrated systems [1,2,3,4,5,6,7,8,9,10,11,12]. To implement a MCML suitable for low voltage operation, a folded strategy, which provides much better performance than the triple tail solution, was presented in [30]. Other design approaches were presented which can allow a minimum supply voltage lower than the one of both the triple tail MCML and the folded MCML (FMCML), but they result advantageous when the gate fan-in is higher than three. The approach named multiple-tail current mode logic (MTCML) [31] provides a shallow depth (based on a different kind of folding with respect to the one used in the FMCML of [30]) and could halve the number of stacked stages, or even further reduce it, but for gate fan-in higher than three it cannot in general achieve a minimum supply voltage as low as the one of a MCML inverter.
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