0.37 mS/μm In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

Abstract

InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∗</sup> ) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL) [1,2]. Most reported InGaAs MOSFETs [3, 4] have ≥ 10 nm channel thickness. The source/drain (S/D) junctions must be very shallow (~5nm) with abrupt vertical and lateral profiles, yet extremely low (~20Ω-μm) source access resistance and consequently very low (~0.3 Ω-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) contact and (~500Ω) sheet resistivities are required to minimize degradation of the drive current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> ) and transconductance g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> [1]. Such parameters are difficult to achieve in InGaAs by ion implantation of the N+ S/D, particularly if an InAlAs bottom confinement layer is used. S/D contacts must be self-aligned to the gate, yet there is no known equivalent of self-aligned silicides in III–V materials. Addressing these requirements, we had reported [5, 6] InGaAs MOSFETs with self-aligned S/D access regions and self-aligned metal contacts formed by MBE regrowth and in-situ metal deposition, though these showed low 0.02 mS/μm transconductance. Here we report greatly improved devices with 0.37 mS/μm transconductance at 0.8 μm L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> .