Abstract

This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K The delay per stage (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ), the static current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STAT</sub> ), the dynamic current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DYN</sub> ), the power dissipation (P) and the phase noise (L(f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> )) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> =179ps), static current (23.55nA/stage), power dissipation (2.13μW) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) reduced to 0.9 V.

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