具有加強轉換增益及雜訊相消機制的 V-band四倍頻器

Abstract

For the reason that the recent trend of high data-rate transmission operating at V-band, this thesis aims at the design of a low-power frequency quadrupler on the application of V-band system such as a local oscillator signal for the up-conversion mixer. Moreover, the frequency quadrupler we proposed is by use of sub-harmonic mixing to improve the efficacy. Through the nonlinear analysis in detail and experiment result, we can demonstrate a truth that the generation efficiency is enhanced. The quadrupler circuit is designed and fabricated in TSMC 90nm CMOS technology. The input center frequency is 12.5 GHz. The measured output power level with an input signal of 8 dBm is -20 dBm( the date contains a loss of 3dB by differential-to-quadrature circuit and a loss of 9.5 dB due to the output buffer.), and the DC power consumption is 2.8mW. In respect of spurs rejection, the corresponding HRRs of f0. 2 f0, and 3 f0 are 53.5, 29.2, and 43 dBc, respectively. In addition, the measure date also verify our proposed architecture get 4 to 7 dB higher than the merely direct generation from the forth-order derivative, which is in a fair comparison III of equal power consumption with each other. Moreover, the DC power consumption is merely 3mW, which is lower than prior works.