Abstract
본 논문에서는 IEEE 802.11n 무선 랜 표준에 규정된 3가지 블록길이(648, 1296, 1944)와 4가지 부호율(1/2, 2/3, 3/4, 5/6)을 지원하는 LDPC 복호기를 최소합 알고리듬과 layered 복호방식을 적용하여 설계하였다. 검사노드 값과 패리티 검사 행렬 정보의 효율적인 저장방법을 통해 메모리 용량을 최소화하였으며, 또한 효율적인 검사노드 메모리 어드레싱 방법을 적용하여 stall 없이 메모리 읽기/쓰기가 가능하도록 하였다. 설계된 회로는 FPGA 구현을 통해 하드웨어 동작을 검증하였으며, <TEX>$0.18-{\mu}m$</TEX> CMOS 셀 라이브러리로 합성한 결과 219,100 게이트와 45,036 비트의 메모리로 구현되었고, 50 MHz@2.5V로 동작하여 164～212 Mbps의 성능을 갖는 것으로 평가되었다. This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a <TEX>$0.18-{\mu}m$</TEX> CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.
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