Ηλεκτρονικές διατάξεις υψηλών συχνοτήτων για ασύρματα συστήματα ευρείας ζώνης

Abstract

In this dissertation we propose, study and develop alternative topologies for two of the most important blocks of a Front-End, the Local Oscillator and the Low Noise Amplifier. We are mainly concerned with the analysis of various local oscillator topologies, studying the phase noise and the injection-locking performance of oscillators and phase-locked loops. The overall performance of the experimental design demonstrates the applicability of the proposed approach to the development of dual-band synthesizers (2.4 GHz and 5.2 GHz), which constitute very important subsystems for modern multiband/multistandard transceivers in WLAN applications. We propose and develop an injection locked oscillator (ILO) and investigate the ability to operate simultaneously as a mixer resulting in a multifunctional circuit. The proposed circuit topology operates as: a) a free-running oscillator, b) both an injection-locked oscillator and a subharmonic injection-locked oscillator (s-ILO), c) both a self-oscillating mixer and a harmonic self-oscillating mixer (h-SOM), and d) a subharmonic injection-locked self-oscillating mixer (s-ILSOM). We propose and develop a different approach for ILPLL design at 5 GHz by applying a technique used in optical communications. We newly address the phase-noise analysis using the loop linear model and compare the results with previously reported work. Furthermore, we address the phase noise improvement of subharmonic ILPLLs, especially for the 5-GHz band. Theoretical analysis and computer calculations demonstrate an improved performance for phase noise and power consumption. We present the analysis and experimental evaluation of a modified dual-loop phase locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimisation of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration. For all the proposed topologies we present the mathematical analysis and calculated results for the phase noise. Measurement results illustrate the validity of the proposed analyses, demonstrate the main characteristics, and confirm the feasibility of the proposed systems. Finally, a bipolar Low Noise Amplifier (LNA) is designed in this thesis. The IC contains the LNA core, an externally programmed bias network and an image rejection filter. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). Furthermore, the chip can be powered down by sending an appropriate bit stream to the bias network.