Abstract
We propose a 100 GHz sub-harmonic injection locked oscillator (ILO) based Phase-Locked Loop (PLL) in CMOS for use in low power Millimeter-Wave (mm-Wave) and sub-Terahertz (THz) phased-array systems. PLL parameters for an imaging system are derived. Mixed-mode simulation to enhance simulation speed has been done with custom Verilog-A models for the PFD/CP/divider and circuit schematic of the ILO. PLL with a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> sub-harmonic ILO at 101 GHz driving a 50 Ω load is shown. Simulated using 1.1 V supply, the PLL phase noise is -76.5 dBc/Hz @ 1 MHz offset, frequency tuning range of ILO is 7 GHz, output power is -9.1 dBm at the load, and power consumption is 14.4 mW. The circuits are implemented in standard digital 65 nm CMOS, enabling high level of on-chip integration.
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