Abstract
This paper introduces a technique for scalable functional verification of cache coherence protocols that is based on the verification method, which was previously developed by the author. Scalability means that verification efforts do not depend on the model size (that is, the number of processors in the system under verification). The article presents an approach to the development of formal Promela models of cache coherence protocols and shows examples taken from the Elbrus-4C protocol model. The resulting formal models consist of language constructs that directly reflect the way protocol designers describe their developments. The paper describes the development of the tool, which is written in the C++ language with the Boost.Spirit library as parser generator. The tool automatically performs the syntactical transformations of Promela models. These transformations are part of the verification method. The procedure for refinement of the transformed models is presented. The refinement procedure is supposed to be used to eliminate spurious error messages. Finally, the overall verification technique is described. The technique has been successfully applied to verification of the MOSI protocol implemented in the Elbrus computer systems. Experimental results show that computer memory requirements for parameterized verification are negligible and the amount of manual work needed is acceptable.
Highlights
Shared memory multiprocessors constitute one of the most common classes of highperformance computer systems
According to the results obtained by the author in this and the previous works, the proposed verification technique consists of the following steps (Fig. 4): 1. Development of a concrete Promela model of the cache coherence protocol under verification
The proposed method was used to verify the MOSI family cache coherence protocol implemented in the Elbrus-4C computer system
Summary
Shared memory multiprocessors constitute one of the most common classes of highperformance computer systems. Burenkov V.S. A Technique for Parameterized Verification of Cache Coherence Protocols. Microprocessor developers design and implement in hardware cache coherence protocols [2]. The widely recognized method for protocol verification is model checking [3]. It is fully automated, but suffers from a principal drawback – it is not scalable due to the state space explosion problem. Previous articles of the author [5,6,7,8] presented a method for parameterized verification of cache coherence protocols. The author successfully applied the method to verification of the cache coherence protocol of the Elbrus-4C computing system.
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