Abstract

The article considers the problems of analyzing DC-DC voltage converters and analyzes the advantages, disadvantages, as well as the scope of full switched and averaged continuous models of the converters. The feasibility of using the complex of two models (full switch model and averaged continuous model) for analyzing their operation is proved. The general approach to the construction of continuous models of DC-DC voltage converters based on state-space averaging method is considered. Disadvantages of the averaged models using a classic approach are shown. The relevance of the development of universal continuous models of DC-DC converters is substantiated. The possibility of creating such models using averaged models of PWM switching structure included in the DC-DC voltage converter is shown. Analyzed the typical structure of the switch-mode power supply with feedback. An averaged model of the switching structure is proposed, basing on which continuous models of DC-DC converters with any topology can be built. The processes occurring in this switching structure in the mode of continuous and discontinuous choke current are analyzed. A method for constructing continuous models of the main types of DC-DC voltage converters based on switching structure averaged model is proposed. The adequacy of continuous models obtained by this method has been proven. The results of modeling transients on the continuous and full switch models for inverting voltage regulator are demonstrated. The possibility of accounting in the model of active resistances of switches and cumulative choke is shown. The possibility of using the proposed model to obtain the open loop transfer functions is demonstrated, in particular, the characteristics of the duty factor - output voltage. These transfer functions can be used to synthesize control system compensating circuits of the switch-mode power supply. The possibility of using a single generalized averaged model of the switching structure to build continuous models of converters with complex topology using both the Voltage Mode and Current Mode is shown. This creates prerequisites for developing a universal averaged continuous model for DC-DC converter based on this principle

Highlights

  • Дальнейшим развитием представленной в статье усредненной модели SD-структуры являются ее адаптация для режима управления Peak Current Mode и создание универсальной усредненной модели широтно-импульсного модулятора (ШИМ)-модулятора, способной реализовывать как режим Voltage Mode, так и режим Peak Current Mode

  • The article considers the problems of analyzing DC-DC voltage converters and analyzes the advantages, disadvantages, as well as the scope of full switched and averaged continuous models of the converters

  • The general approach to the construction of continuous models of DC-DC voltage converters based on state-space averaging method is considered

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Summary

Gs dD ds Fs L

Для SD-структуры средний ток управляемого ключа S в режиме непрерывных (CCM – Continuous Conduction Mode) и разрывных (DCM – Discontinuous Conduction Mode) токов дросселя с классической обратной связью по напряжению (Voltage Mode) может быть определен аналогично [8]: is. Для базовых регуляторов (понижающего, повышающего и инвертирующего) это ток iL дросселя L1 3 среднее напряжение на диоде vcs,d создается нелинейным зависимым источником электродвижущей силы Ecd. Для вычисления относительной длительности проводимости dD диода D необходимо определить напряжение vL на дросселе L1 при включенном ключе S [3, 5] через средние значения напряжений внешних узлов модели. Для рассматриваемых регуляторов это будет разность средних потенциалов узлов “s” и “сs”: vL = vs,cs = vs − vcs. В непрерывной модели значение dD задается нелинейным зависимым источником напряжения Ed2. Структурная схема непрерывной модели стабилизатора напряжения на основе понижающего (BUCK) регулятора для режима Voltage Mode представлена на рис. Структурная схема непрерывной модели стабилизатора напряжения на основе понижающего (BUCK) регулятора для режима Voltage Mode представлена на рис. 5

Vref ds d
CCpp RL
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