Abstract
Abstract. The paper describes a method for constructing test oracles for memory subsystems of multicore microprocessors. The method is based on using nondeterministic reference models of systems under test. The key idea of the approach is on-the-fly determinization of the model behavior by using reactions from the system. Every time a nondeterministic choice appears in the reference model, additional model instances are created and launched (each simulating a possible variant of the system behavior). When the testbench receives a reaction from the system under test, it terminates all model instances whose behavior is inconsistent with that reaction. An error is detected if there is no active instance of the reference model. The suggested method has been used in verification of the L3 cache of the Elbrus-8C microprocessor and allowed to find three bugs. Keywords: multicore microprocessors; cache memory; memory consistency; coherence protocols; functional verification; model-based testing; testbench automation; test oracle; Elbrus-8C.
Highlights
A key feature of modern microprocessor architectures is multicoreness, which is implementation of several processing units, so-called cores, on a single chip
Every time a nondeterministic choice appears in the reference model, additional model instances are created and launched
A reference model and the test oracle are divided into three levels: (1) the operation level, (2) the cache line level, and (3) the memory subsystem level
Summary
A key feature of modern microprocessor architectures is multicoreness, which is implementation of several processing units, so-called cores, on a single chip. At the heart of such mechanisms is a coherence protocol, a set of rules that governs interactions between storage devices and guarantees memory consistency for all possible data access scenarios [1]. A widely accepted approach to ensure correctness of complex hardware designs is simulation-based verification, or testing. A test system, known as a testbench, solves two main tasks: first, it generates a stream of stimuli; second, it checks whether the design behavior satisfies the requirements [3]. This paper addresses the second problem, i.e. checking reactions of a memory subsystem in response to an arbitrary series of stimuli; it introduces a method for constructing test oracles (reaction checkers) based on high-level reference models of memory subsystems.
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