Post-Silicon Verification of Multi-Core Processors

Abstract

In the past four decades, microprocessor architectures have evolved from relatively simple circuits to highly optimized, performance-oriented designs with multiple parallel execution pipelines, running at gigahertz frequencies. However, in the beginning of the 21st century, designers realized that processor frequencies could no longer be increased,mainly due to power density constraints. Thus, to keep responding to users’ demand for higher performance, they turned towardsmulti-core designs. In these architectures, multiple central processing units (cores) perform independent computations in parallel, communicating through on-chip interconnect and shared memory hierarchies. Because of the shorter and simpler pipelines and lower operation frequencies of individual cores, multi-core chips deliver much higher multi-threaded performance and demand lower power than traditional architectures. Today, with two- and four- core processor systems being mainstream, this trend continues as manufacturers roll out prototypes and application-specific systems with as many as 80 processing elements. Yet, the verification of multi-core designs has become even more complex when compared to uniprocessors, due to the concurrent interaction among cores, often leading to non-deterministic behavior. Since the majority of designs rely on shared memory protocols for inter-core communication, issues such as cache coherence and memory consistency have become dominant in the multi-core verification process. At early design stages, powerful formal tools can be wielded to ensure correctness of high-levelmodels of these protocols. Verification of the implementations of cache coherence and memory consistency, however, still remains challenging, especially in the post-silicon domain, where much of the device’s internals cannot be observed. In this chapter, we briefly overview the history and basic structure of state-of-the-art multi-core architectures and discuss the challenges of their verification. We will also overview two post-silicon solutions designed for validation of cache coherence protocols and memory consistency, setting the tone for the next chapter, where we present a comprehensive low-cost framework for the post-silicon validation of these aspects.