Zybo Board Research Articles

An Elliptic Curve Menezes–Qu–Vanston-Based Authentication and Encryption Protocol for IoT

The exponential growth of the Internet of Things (IoT) has led to a surge in data generation, critical for business decisions. Ensuring data authenticity and integrity over unsecured channels is vital, especially due to potential catastrophic consequences of tampered data. However, IoT’s resource constraints and heterogeneous ecosystem present unique security challenges. Traditional public key infrastructure offers strong security but is resource intensive, while existing cloud-based solutions lack comprehensive security and rise to latency and unwanted wastage of energy. In this paper, we propose a universal authentication scheme using edge computing, incorporating fully hashed Elliptic Curve Menezes–Qu–Vanstone (ECMQV) and PUF. This approach provides a scalable and reliable solution. It also provides security against active attacks, addressing man-in-the-middle and impersonation threats. Experimental validation on a Zybo board confirms its effectiveness, offering a robust security solution for the IoT landscape.

Edge Detection on Field Programmable Gate Array (FPGA)

Edges are significant local changes in the image and are very important features for analysing images. Edges typically occur on the boundary between two different regions in an image. An edge in an image is a significant local change in the image intensity, usually associated with a discontinuity in either the image intensity or the first derivative of the image intensity. Edge detection is one of the tools that can be used in many image processing applications for withdrawing information from image. Sobel edge detection is one of the operators that operate on gradient based edge selection methods to find edge pixels in the image. This report proposed an implementation of Sobel edge Detection algorithm to find the pixels in grayscale images. We present a video streaming architecture and IP implementation using high level synthesis. A video with 720p resolution streamed from the HDMI source and real time edge detected video captured on another monitor. For implementation, ZYBO board or kit is used with Vivado software with 2018.3 V, which has provided adequate peripherals for implementation.

FPGA implementation of high‐speed tunable IIR band pass notch filter for identification of hot‐spots in protein

SummaryLocalization of hot spots in a protein sequence is an important problem for understanding complex 3D structure of amino acid sequence (due to which biological functionality of protein is performed by their mutual interactions). Several digital signal processing (DSP) techniques like digital filtering, wavelet, and Fourier transforms have been used for finding the hot‐spot locations. Fast processing of these longer protein sequences is desirable. Field Programmable Gate Array (FPGA) implementation of Infinite Impulse Response (IIR) band pass notch (BPN) digital filter (tuned automatically by characteristics frequency of protein family) is carried out in this paper for further speed‐up of this protein analysis process. Performance of proposed filter system (implemented on Zynq series Zybo board FPGA) is further improved using retiming, which has significantly increased the maximum clock frequency from 34.304 to 54.812 MHz. Simulation of both MATLAB and FPGA hardware implementation for BPN IIR filter is executed on 10 protein functional groups. The simulation results predict the same hot‐spots locations as mentioned in ASEdb data base, but the Hardware BPN IIR filter (proposed in this paper) is 190 to 278 times faster as compared to its MATLAB counterpart. Some additional new hot‐spot locations (not mentioned in ASEdb data base) have been determined by our proposed hardware filter, which can be the probable hot‐spots for newly identified proteins.

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

Thai Voice-Controlled Analysis for Car Parking Assistance in System-on-Chip Architecture

This paper introduces an analysis of Thai speech recognition for controlled car parking assist in the system-on-chip architecture. The objective is to investigate the male and female voice command signals, including Thai and English words, issued by the native Thai users. Hardware and software co-design by the Xilinx VIVADO are designed on an ARM multicore processor and a reconfigurable system on a ZYBO board. The experiments for Thai and English word recognition are conducted by using the Mel-frequency cepstral coefficient approach and presented in the form of spectrograms. The comparison of a voice command via Bluetooth and a reference command stored on an SD card and the ZYBO embedded board on a miniature electric vehicle is verified with the Pearson’s correlation coefficient (PCC). The experimental results show the accuracies of the received Thai/English, male/female, and indoor/outdoor voice commands as compared with the reference voice commands in the noisy surroundings. Hence, our system can support Thai/English and male/female voice commands to perform a set of actions for maneuvering a car by the PCC.

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

SummaryThe discrimination of exons from introns in the DNA sequence of a eukaryotic gene is important to understand the functionality of protein formation inside a living organism. Several signal processing techniques involving transforms and filtering have been used to identify the exon regions by exploring the periodicity‐3 property. Fast processing of massive DNA sequences is desirable to detect the disease‐causing mechanism, which is helpful to prepare individual‐centric drugs. In this manuscript, a hardware implementation is carried out for the direct form‐II structure of the infinite impulse response anti‐notch filter to achieve the fast processing of the DNA sequence. Implementation result on Zynq‐series (Zybo board) Field Programmable Gate Array (FPGA) reveals that the proposed implementation is capable to identify the exon regions of five benchmark eukaryotic genes. The FPGA implementation has achieved a maximum clock frequency of 34.629 MHz, which is further improved to 54.41 MHz using the retiming concept. Compared with MATLAB 2014a simulation, the proposed FPGA implementation has achieved similar accuracy with 39 to 43 times faster computing time for the five benchmark data sets. Further, an Application Specific Integrated Circuit (ASIC) implementation is carried out in the CADENCE Register Transfer Level (RTL) compiler tool with GPDK 90‐nm technology, due to which the hardware anti‐notch filter is 120 to 133 times faster compared with its MATLAB counterpart while maintaining the comparable accuracy.

VLSI implementation of anti‐notch lattice structure for identification of exon regions in Eukaryotic genes

In a Eukaryotic gene, identification of exon regions is crucial for protein formation. The periodic-3 property of exon regions has been used for its identification. An anti-notch infinite impulse response (IIR) filter is mostly employed to recognise this periodic-3 property. The lattice structure realisation of anti-notch IIR filter requires less hardware over direct from-II structures. In this study, a hardware implementation of IIR anti-notch filter lattice structure is carried out on Zynq-series (Zybo board) field programmable gate array (FPGA). The performance of hardware design has been improved using techniques like retiming, pipelining and unfolding and finally assessed on various Eukaryotic genes. The hardware implementation reduces the time frame to analyse the DNA sequence of Eukaryotic genes for protein formation, which plays a significant role in detecting individual diseases from genetic reports. Here, the performance evaluation is carried out in MATLAB simulation environment and the results are found similar. Application-specific integrated circuit (ASIC) implementation of the anti-notch filter lattice structure is also carried out on CADENCE-RTL compiler. It is observed that the FPGA implementation is 31 to 34 times faster and ASIC implementation is 58 to 64 times faster compared to the results generated by MATLAB platform with similar prediction accuracy.

Implementation of Visible Light Communication for Data Acquisition using System on Chip

Visible light communication is the future of the globe communication having applications in trust areas like V2V communication, Vehicle to infrastructure, medical domain etc., We propose a design for a computer architecture in data acquisition system using system on chip to transmit the image data and the same is received in the receiver side. The proposed mode consist of hardware and software task.The hardware task is designed using zybo board which is soc board and Xilinx is used as an interface between hardware and the system. The proposed mechanism proves to have better data acquisition capability than other models at a higher data rate.

Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>