Zero Temperature Coefficient Point Research Articles

Achieving Zero-Temperature Coefficient Point Behavior by Defect Passivation for Temperature-Immune Organic Field-Effect Transistors.

Organic field-effect transistors (OFETs) have broad prospects in biomedical, sensor, and aerospace applications. However, obtaining temperature-immune OFETs is difficult because the electrical properties of organic semiconductors (OSCs) are temperature-sensitive. The zero-temperature coefficient (ZTC) point behavior can be used to achieve a temperature-immune output current; however, it is difficult to achieve in organic devices with thermal activation characteristics, according to the existing ZTC point theory. Here, the Fermi pinning in OSCs is eliminated using the defect passivation strategy, making the Fermi level closer to the tail state at low temperatures; thus threshold voltage (VT) is negatively correlated with temperature. ZTC point behaviors in OFETs are achieved by compensation between VT and mobility at different temperatures to improve its temperature immunity. A temperature-immune output current can be realized in a variable-temperature bias voltage test over 50000s by biasing the device at the ZTC point. This study provides an effective solution for temperature-immune OFETs and inspiration for their practical application.

On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs

In this article, we propose an explanation of the origin of the zero-temperature coefficient (ZTC) in fully depleted-silicon on insulator (FD-SOI) MOSFETs capacitance curves from room to cryogenic temperature. It is demonstrated that the ZTC is a natural consequence of the Fermi–Dirac function controlling the carrier population. Moreover, based on transport analysis in linear region, it is proven that the ZTC point is preserved in the drain current transfer characteristics only if the mobility varies as the reciprocal temperature, i.e., if it is purely phonon scattering-limited. The inclusion of other defective scattering mechanisms dispels the ZTC point. Finally, the model developed is validated by some TCAD simulations down to deep cryogenic temperatures.

Determining the Zero-Temperature-Coefficient Point From Device Simulation to Circuit for Improving Temperature Variation Immunity

Thermal issue emerges as one of the critical reliability concerns in integrated circuit design, especially for advanced technology. To improve the temperature immunity and reduce the thermal-related timing guard bands in digital circuits, in this work, we offer a new insight into the zero-temperature-coefficient (ZTC) based design strategy featuring minimizing the temperature-induced delay variation. An effective current-based method to facilitate the ZTC point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> ) determination for standard cells is developed, which is demonstrated on advanced gate-all-around (GAA) nanosheet (NS) FETs from 300 to 425 K using the calibrated TCAD simulation. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> dependencies on the signal input slew rate, output capacitance, and self-heating effects (SHEs) are further investigated from the perspective of the effective current by tracing the voltage trajectory. The mixed-mode TCAD simulation results show that the frequency variation of ring oscillator (RO) reduces nearly ten times when operating near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> and great power-performance trade-offs can also be achieved. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> determination for standard cells combined with the compensation effect among different standard cells benefits selecting the optimal zero-temperature-delay (ZTD) point in the target path, thereby helping to implement a robust digital design against temperature variation.

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ) is more critical at higher drain-to-source voltages (V DS). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.

Zero Temperature Coefficient behavior for Ellipsoidal MOSFET

The zero temperature coefficient (ZTC) is investigated by three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (Ag) and bias condition (BC). In this work an improved simple model which predicts the ZTC point taking into account only the mobility degradation factor (c) and threshold voltage (Vth) parameters as function of temperature is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the mobility degradation factor. Although simple, the model predictions present a good agreement with the numerical simulations results.

Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures

Introduction: There is a growing interest in new electronic systems that must operate at high temperature (T) for automotive and space electronics, etc. To reach this purpose new device architectures have been proposed, such as the Gate-All-Around, double-gate, Multigate SOI MOSFETs, etc. [1]. However, there is a new concept, still little explored by the integrated circuits industries, which is based on the simple change of the gate geometry of MOSFETs [2]. This pioneering technique is capable for boosting the electrical performance of MOSFETs, thanks to two new effects of these structures, called “Longitudinal Corner Effect” (LCE) and “PArallel connection of MOSFETs with Different channel Lengths Effect” (PAMDLE) [2]. The Ellipsoidal layout style for MOSFET (EM) [4] is an example this new concept. Thus, this manuscript performs a comparative study by three-dimensional (3D) numerical simulations of the effects caused by the high T (300K-573K) in main electrical parameters of the EM in relation to the Rectangular MOSFET (RM) counterpart, regarding the same gate area, channel width and bias conditions. Furthermore, for the first time, is analyzed the electrical behaviors of LCE and PAMDLE in these conditions. Based on these results, we conclude that the EM always presents a better electrical performance {two times higher for the drain current normalized [IDS/(W/L)] and 77% higher for the transconductance normalized [gm/(W/L)]} than that found in the RM counterpart at high T. Besides, the LCE and PAMDLE always keep actives in the EM as the T increases. Results: The 3D numerical simulations were performed by using of the Sentaurus TCAD/Synopsys. The doping concentrations of the drain/source and channel are 1019cm-3 and 1017cm-3, respectively, gate thin-oxide thickness is 4.2nm and work-function of polysilicon is 4.15eV. The threshold voltages for both devices are equal to 50mV in room T.Fig.1 shows the IDS/(W/L) as a function of gate voltage (VGS) for different temperatures of the EM (Fig.1a) and RM counterpart (Fig.1b). Based on results, we observe that the Zero Temperature Coefficient (ZTC) biases of the EM and RM (VZTC) are practically similar (difference of 6%), while the EM IDS/(W/L) in the ZTC point is 142% higher than the one measured of RM, thanks the LCE and PAMDLE present in the EM structure.Fig.2 illustrates IDS/(W/L) as a function of drain bias (VDS) considering different temperatures. The EM IDS/(W/L) in all temperatures studied, considering the triode and saturation regions, are always higher (2 times higher) than the ones observed in RM counterpart.Based in these previous results, Fig.3 presents the gmmax/(W/L) and IDS_SAT/(W/L) as a function of the T. We have observed that the gmmax/(W/L) (72% and 81% for 300K and 573K, respectively, Fig.3a) and EM IDS_SAT/(W/L) (2 times higher, Fig.3b) are always higher than those found in the RM counterpart thanks to LCE and PAMDLE and they reduce with the T increases. Therefore, we have concluded that the LCE and PAMDLE are always active in this huge range of high temperatures, according Fig.4, which the resultant longitudinal electric field (RLEF) in the center of the channel length (L) of the EM (Fig.4a) reduces 6% as the T varies (300K-573K). The maps of the EM RLEF lines are illustrated in Fig.4b for different 2 Ts, wherein the width of the depletion region (d) composed by the source/channel regions reduces as the T increases. Furthermore, Fig.4c illustrates de map of the EM IDS lines which are curves near to the edges and straight in the center of the L, due to the interactions of the longitudinal electric field components (3 in the straight defined by the foci of the ellipse and 2 out of it). Conclusion: We have concluded that the LCE and PAMDLE are always actives as the T increases and consequently are capable of boosting the EM electrical performance in comparison to the one of the RM counterpart, regarding all T studied. Furthermore, as the T increases, the magnitude of the RLEF reduces 6%, because of the reduction of the Fermi Potential that defines the surface potential. Besides, we observe that the width of the region where the RLEF acts along the channel region of the EM increases due to reduction of depletion region width between source/channel regions (from d1 to d2), as the T increases. Acknowledgment: We thank to the São Paulo Research Foundation (FAPESP), grant #2017/10718-7 and CNPq, grant #308702/2016-6 for financial support.

Impact of Gate Dielectric Material on Basic Parameters of MO(I)SHEMT Devices

Recently the high electron mobility transistors (HEMT) have drawn the attention of the scientific community for power electronic applications thanks to their wide bandgap and consequently high breakdown voltage (1-3). A new metal oxide/insulator semiconductor high electron mobility transistor (MOSHEMT) appears in order to minimize the leakage current as reported in (4). In this work, the basic parameters of MOSHEMT are evaluated experimentally for different gate insulators (10nm of Al2O3 and 5nm of SiNx).From the transfer curves presented in figure 1, one can notice a shift in the threshold voltage and different hysteresis behavior when comparing both insulators. The hysteresis analysis shows a better behavior for SiNx devices, which present negligible hysteresis values. Figure 2 presents the hysteresis width extracted from devices with Al2O3 as a function of gate length for different drain bias. Although usually the Vth variation is associated with positive charge trapping, which causes a negative Vth shift, in this case the opposite Vth variation was observed. This positive Vth shift may also be related with a degradation of the on-resistance, i.e., a higher voltage is required to obtain the same current level, as reported in (3). As the drain voltage and consequently the drain current increase, the Vth shift becomes smaller reducing the hysteresis values, as can be seen in figure 2.Focusing on the threshold voltage variation between devices with different gate dielectrics, although both the gate insulator thicknesses and the permittivity impact on the threshold voltage (Vth) of the transistor in opposite direction (5), the dominant factor of the Vth shift, in this case, is a negative linear relation between Vth and the dielectric thicknesses. The MISHEMT with 5 nm of SiNx presents a Vth almost 2V higher than MOSHEMT with 10nm of Al2O3.In addition to the better Vth value (closest to the normally-off device), SiNx dielectric transistors are less affected by the short channel effect (SCE) when compared to devices with Al2O3, as can be observed in figure 3. From Fig. 3 it is possible to notice that reducing the channel length (Lg) from 600nm to 200nm, the threshold voltage for transistors with SiNx dielectric (figure 3B) drops 175mV while for devices with Al2O3 layer (figure 3A) this reduction reaches 450mV. Considering DIBL (|Vthlinear – Vthsat|/ VDSsat – VDSLinear) with VDSsat=2V, it is also observed that for both splits the DIBL starts to degrade for Lg = 400 nm, however the values and the degradation of DIBL are much higher for devices with Al2O3 than for devices with SiNx dielectric. This behavior can be related to the thinner dielectric and better coupling between the gate and the GaN layer.When the MOSHEMTs were evaluated at high temperatures (from 25ºC to 150ºC), two different behaviors were obtained. The transfer characteristic of MOSHEMT with Al2O3 layer (figure 4A) presents an expected behavior, showing the zero temperature coefficient point (VZTC) due to the competition between the threshold voltage reduction and mobility degradation, while for the MISHEMTs with SiNx layer the VZTC was not found. In order to explain this unexpected behavior the threshold voltage and transconductance were evaluated (figures 5 and 6).MOSHEMTs with Al2O3 gate present a reduction of the threshold voltage as the temperature increases (figure 5A) due to the reduction of the fermi potential, for all analyzed channel lengths. However, for SiNx MISHEMTs Vth is reduced when the temperature increases from 25ºC to 50ºC, but for higher temperatures Vth starts to increase again creating a rebound effect. The threshold voltage anomalous behavior can be explained by the double conduction of the device which leads us to extract an effective Vth. This double conduction can only be observed when we evaluate the transconductance curve of the MISHEMTs (figure 6). It is possible to observe that for temperatures higher than 50ºC the transconductance curve presents two different slopes before the maximum value, representing two different conduction channels. Figure 6B shows the transconductance and drain current as a function of gate voltage at 100ºC and it is easy to see the two different slopes representing the two different threshold voltages, due to the turn on/off of the SiNx/AlGaN inversion layer. Looking for the transition point between both conductions, we can also observe a small peak in the drain current. Figure 1

Tradeoff between the transistor reconfigurable technology and the zero-temperature-coefficient (ZTC) bias point on BESOI MOSFET

A tradeoff between transistor reconfigurability and a Zero Temperature Coefficient (ZTC) bias point was observed and analyzed for Back Enhanced SOI (BESOI) MOSFET for the first time. The ZTC is observed only for BESOI MOS with aluminum Source/Drain (S/D) electrodes (ohmic contact with the channel) while the transistor reconfigurability is present only for BESOI MOS with nickel S/D electrodes (Schottky contact). This tradeoff is discussed and demonstrated experimentally and by numerical simulations.For ohmic S/D contacts, the temperature-independent point (ZTC) happens for front gate bias from −2.44 V to −0.61 V (for a back gate VGB changing from −15 V to −30 V respectively). Following other technologies, such as UTBB and FinFET, this point represents the compensation between the threshold voltage decrease and the mobility degradation when increasing the temperature. However, for S/D to channel Schottky contacts, there is no ZTC point and only for this condition the BESOI presents a reconfigurable behavior, i.e., p-type and n-type BESOI behavior can be observed by applying different VGB.The BESOI CMOS inverter built with nickel S/D electrodes was used to confirm the transistor reconfigurability. Therefore, depending on the S/D electrodes material, a reconfigurable device or a ZTC bias point behavior on BESOI MOSFET is observed, which is useful for different applications at the same chip.

A 0.3–1.2 V Schottky-Based CMOS ZTC Voltage Reference

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3 V up to 1.2 V and outputs three different reference voltages using Standard- $V_{T}$ (SVT), Low- $V_{T}$ (LVT), and Zero- $V_{T}$ (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13- $\mu \text{m}$ CMOS process show a worst-case normalized standard deviation $(\sigma /\mu)$ of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/°C over the full commercial temperature range. At room temperature (25 °C), line sensitivity in the ZVT VR is just 1.3%/100 mV, over the whole supply range. The proposed reference draws around 5 $\mu \text{W}$ and occupies 0.014 mm2 of silicon area.

Low-Voltage Current and Voltage Reference Design Based on the MOSFET ZTC Effect

Most conventional CMOS technologies possess the so-called zero-temperature coefficient (ZTC) operating point where the transistor’s drain current becomes nearly independent of temperature due to the mutual temperature cancellation of threshold voltage and carrier mobility. This paper discusses how this ZTC point can be exploited in the design of current and voltage references with low supply voltages. Besides a theoretical overview regarding the ZTC behavior, a current reference in a standard 0.25- $\mu \text{m}$ CMOS technology operable from 1.3 V is presented. To further explore the possibilities of this approach, a voltage reference with a nominal supply voltage of just 0.5 V is designed and fabricated in a 130-nm technology. Measurement results are given for both circuits.

A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar

Traditional bandgap reference (BGR) is sensitive to process variation and is not suitable for mass production. Consequently, a stacked piece-wise compensated bandgap reference (SPWBGR) with low beta bipolar is proposed, designed and fabricated in the 0.18 μm high-voltage (HV) BCD process. Two stacked BGR (SBGR) cores make up the proposed BGR circuit. Through setting the target reference voltage near the output voltage of SBGR cores, the feedback resistor ratio is reduced and the base current side-effect is significantly decreased. Notably, the SBGR core is implemented by the low beta npn bipolar and it relaxes the requirement for the high beta bipolar. The two SBGR cores are almost identical except for the temperature slope and feedback ratio. The two cores have different zero temperature coefficient (TC) points, one is set at −5 °C, and the other is set at 60 °C, named as SBGRA and SBGRB, respectively. The SBGRA and SBGRB output the same voltage at their zero TC point. The higher voltage of SBGRA and SBGRB is the output voltage. Through the process of tracking the maximum value of different SBGR cores, the proposed SPWBGR achieves 2.6 ppm/°C TC from −40 to 100 °C. As a result, the average TC for five random samples is 5.3 ppm/°C. The line regulation is 2 mV/V from 4.5 to 5.5 V power supply. The current consumption is 6.8 µA. The active area of the proposed BGR is 0.075 mm2.

Highly Reliable Multiport PUF Circuit Based on MOSFET Zero Temperature Coefficient Point

By using processing variations in the unitcircuits of the same structures and design parameters during manufacturing, Physical unclonable function (PUF) generates security keys with characteristic of uniqueness, randomness and unclonability. In this paper, a highly reliable multiport PUF scheme was proposed based on MOSFET Zero temperature coefficient (ZTC) point. It consists of input register, deviation-current generating module, arbiter array and obfuscation circuit. After reconfiguring deviation-current generating module by applying different input challenges, the PUF circuit updates keys without physical replacement. And multi-bit keys can be generated in one clock cycle. In TSMC-LP 65nm CMOS technology, the layout of 64-port reconfigurable PUF occupies 131μm×242μm with custom designing. Experimental results show that the PUF circuit has good statistical characteristic of uniqueness and randomness. It exhibits high reliability of 98.2% with respect to temperature variation from -40°C to 125°C and supply voltage variation from 1.08V to 1.32V, indicating that it can be reliably and effectively used in information security field.

Device behaviour and zero temperature coefficients analysis for microwave GaAs HEMT

Detailed analysis of device behaviour on the zero-temperature coefficient (ZTC) points for microwave GaAs based high-electron mobility transistor is presented by means of on-wafer measurements over the temperatures between −40 and 150 °C. This zero temperature coefficient points found not only in the transfer and transconductance curve but also in intrinsic transconductance gmo, output conductance gds, small signal gain S21, and minimum noise figure NFmin also exhibits ZTC. It is found that the zero temperature coefficients points are impacted by both threshold voltage and drain bias. The transfer current base, ZTCIds moved from 0.1 V to −0.2 V of Vgs trace and transconductance based, ZTCgm moved from −0.3 V to −0.6 V of Vgs trace with the drain bias, Vds varies from 1 V to 5 V. The behaviour of some intrinsic equivalent circuit parameters along with cut-off frequency, ft at both ZTC bias points opens some crucial insight and opportunities in microwave device design for low and high temperature applications.

The investigation of the zero temperature coefficient point of power MOSFET

The paper investigates the zero temperature coefficient (ZTC) point of power MOSFET, based on the output characteristic of power MOSFET, the temperature coefficient of threshold voltage and the carrier mobility. It is found that the gate voltage has a big effect on the ZTC point. The result indicates that there are three types of temperature coefficient under different gate voltage. When the gate voltage is near the threshold voltage, both the linear region and saturation region shows a large positive temperature coefficient. With the increase of gate voltage, the temperature coefficient of the linear region changes from positive to negative, when the saturation region still remains positive, giving rise to the ZTC point. When the gate voltage is high enough, the negative temperature coefficient is present on both the linear and saturation region, resulting in no ZTC point. According to the experimental result, the change of ZTC point as a function of temperature is larger when the gate voltage is higher. The carrier mobility is also discussed, displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.

Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges

This paper is a unique attempt to identify the zero-temperature-coefficient (ZTC) point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a biasing point i.e. ZTC bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on various performance metrics like on current (Ion), off current (Ioff), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd), intrinsic gain (AV) and cut off frequency (fT) is also subjected to extensive analysis. The variation of ZTC point for transconductance (ZTCgm) and drain current (ZTCIDS) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential

A compact zero-temperature coefficient (ZTC) modeling approach is demonstrated for generic MOSFETs. Instead of manually extracting ZTC points through <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> or <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> data over a range of operating temperatures, the ZTC model marks the cross-over ZTC points by Newton-Raphson solutions to the ZTC voltages based on the compact charge/current models. It calculates the ZTC voltages in the accumulation ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ztc,sa</sub> ) and depletion ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ztc,ds</sub> ) regions based on the unified regional modeling of surface potential for the gate capacitance at zero drain bias ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =0). It is extended to the ZTC voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ztc,ds</sub> ) for gate capacitance in the depletion and saturation regions at any <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , and the ZTC voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ztc</sub> ) for drain current in the linear and saturation regions at any <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> . The proposed approach can be adopted to create a process window with constant ZTC contours for different process parameters, such as body doping and gate-oxide thickness at any drain biases. The process windows provide useful information in determining the optimum process parameters and operating voltages for circuit design in ruggedized electronics that operate at high-temperature conditions.

Impacts of Multiple Strain-Gate Engineering on a Zero-Temperature-Coefficient Point

The impacts of zero-temperature-coefficient (ZTC) points of various strained devices is presented in this paper. The current and mobility are reduced at high temperature by phonon scattering. The degree of mobility reduction becomes severe on devices with multiple strain-gate engineering. The reduction of mobility becomes severe as a result of impurity scattering, which results from gate implantation impurities. The ZTC point is decreased by multiple strain-gate engineering due to the decreased Vth.

The zero temperature coefficient in junctionless nanowire transistors

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices.

Improved Analytical Model for ZTC Bias Point for Strained Tri-gates FinFETs

The zero temperature coefficient (ZTC) is investigated experimentally in standard and biaxially strained Tri-gate nFinFETs fabricated on SOI wafers. In this work an improved model to analyze the behavior of the gate-source voltage (VGS) at Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the transconductance degradation factor. Although simple, the model predictions present a good agreement with the experimental results.

The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration

For the first time, analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. New analytical formulations for the linear and saturation regions of DTMOS transistor operation that make certain the drive current to be temperature independent for the ideal gate voltage are developed. The maximum errors of 0.87% and 2.35% in the linear and saturation regions, respectively, confirm a good agreement between our DTMOS ZTC point model and the experimental data. Compared to conventional MOSFET, the lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> (ZTC) with higher overdrive current of DTMOS improves the integrated circuit speed and efficiency for the low-power-consumption concept in green CMOS technology.