Zero Temperature Coefficient Bias Point Research Articles

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks.

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ) is more critical at higher drain-to-source voltages (V DS). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.

Vertical GaN-Based Temperature Sensor by Using TiN Anode Schottky Barrier Diode

Vertical GaN Schottky barrier diode was fabricated as temperature sensor by using a thermally stable TiN anode. The current-voltage characteristics of the diode measured at various temperature present a zero-temperature coefficient (ZTC) bias point of approximately 0.6 V. At the voltage below the ZTC bias point (sub-threshold region), the forward voltage at a fixed current decreases linearly with the increasing temperature, resulting in a sensitivity of approximately 1.3 mV/K. In the reversely biased region, the leakage current also presents temperature-dependent behavior with a sensitivity of approximately 19.7 mA/K regardless of the bias. Those results can be interpreted by the thermionic emission model.

Tradeoff between the transistor reconfigurable technology and the zero-temperature-coefficient (ZTC) bias point on BESOI MOSFET

A tradeoff between transistor reconfigurability and a Zero Temperature Coefficient (ZTC) bias point was observed and analyzed for Back Enhanced SOI (BESOI) MOSFET for the first time. The ZTC is observed only for BESOI MOS with aluminum Source/Drain (S/D) electrodes (ohmic contact with the channel) while the transistor reconfigurability is present only for BESOI MOS with nickel S/D electrodes (Schottky contact). This tradeoff is discussed and demonstrated experimentally and by numerical simulations.For ohmic S/D contacts, the temperature-independent point (ZTC) happens for front gate bias from −2.44 V to −0.61 V (for a back gate VGB changing from −15 V to −30 V respectively). Following other technologies, such as UTBB and FinFET, this point represents the compensation between the threshold voltage decrease and the mobility degradation when increasing the temperature. However, for S/D to channel Schottky contacts, there is no ZTC point and only for this condition the BESOI presents a reconfigurable behavior, i.e., p-type and n-type BESOI behavior can be observed by applying different VGB.The BESOI CMOS inverter built with nickel S/D electrodes was used to confirm the transistor reconfigurability. Therefore, depending on the S/D electrodes material, a reconfigurable device or a ZTC bias point behavior on BESOI MOSFET is observed, which is useful for different applications at the same chip.

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

ZTC bias point of advanced fin based device: The importance and exploration

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges

This paper is a unique attempt to identify the zero-temperature-coefficient (ZTC) point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a biasing point i.e. ZTC bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on various performance metrics like on current (Ion), off current (Ioff), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd), intrinsic gain (AV) and cut off frequency (fT) is also subjected to extensive analysis. The variation of ZTC point for transconductance (ZTCgm) and drain current (ZTCIDS) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

Resolving the bias point for wide range of temperature applications in High-k/Metal Gate nanoscale DG-MOSFET

This article investigates the Zero-Temperature-Coefficient (ZTC) bias point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC bias point is defined as the point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC bias points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications.

Improved Analytical Model for ZTC Bias Point for Strained Tri-gates FinFETs

The zero temperature coefficient (ZTC) is investigated experimentally in standard and biaxially strained Tri-gate nFinFETs fabricated on SOI wafers. In this work an improved model to analyze the behavior of the gate-source voltage (VGS) at Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the transconductance degradation factor. Although simple, the model predictions present a good agreement with the experimental results.

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600°K by using the SILVACO11All product names are trademarks of SILVACO International, 4701 Patrick Henry Drive, Santa Clara, CA, USA. TCAD tools. In particular, we have studied their current–voltage characteristics (ID–VGS and ID–VDS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.