Zero-suppressed Decision Diagrams Research Articles

Digital twin-based fault tolerance approach for Cyber–Physical Production System

Cyber–Physical Production Systems (CPPSs) as distributed Systems of Systems (SoS) are at the center of attention from different industries. CPPSs face different categories of errors. These errors will cause failures of the entire production chain. To handle this concern, production systems should be converted into fault-tolerant production systems. To present such systems, a fault tolerance approach was developed to help possible faults prediction and detection of faults causes in this study. Also, the increasing complexity and uncertainty of CPPS call for Digital Twin (DT)-based fault tolerance approach. The proposes approach uses an extraction module to extract the faults signatures efficiently. Based on all extracted faults, appropriate responses could be generated through reliable faults patterns prediction. This method is provided using Fault Tree Analyzer (FTA), Zero-suppressed Decision Diagram (ZDD), and Support Vector Machine-Adaptive Neuro-Fuzzy Inference System (SVM-ANFIS) structure. The results based on digital twin-based CPPS of the food production system as a use case show that the proposed approach can predict reliable faults signatures to prevent failures and make a much reliable production system. Also, this method can guarantee that CPPS is up and running with optimal levels at all times.

Chain Reduction for Binary and Zero-Suppressed Decision Diagrams

Chain reduction enables reduced ordered binary decision diagrams (BDDs) and zero-suppressed binary decision diagrams (ZDDs) to each take advantage of the others' ability to symbolically represent Boolean functions in compact form. For any Boolean function, its chain-reduced ZDD (CZDD) representation will be no larger than its ZDD representation, and at most twice the size of its BDD representation. The chain-reduced BDD (CBDD) of a function will be no larger than its BDD representation, and at most three times the size of its CZDD representation. Extensions to the standard algorithms for operating on BDDs and ZDDs enable them to operate on the chain-reduced versions. Experimental evaluations on representative benchmarks for encoding word lists, solving combinatorial problems, and operating on digital circuits indicate that chain reduction can provide significant benefits in terms of both memory and execution time.

Using ZDDs in the Mapping of Quantum Circuits

A critical step in quantum compilation is the transformation of a technology-independent quantum circuit into a technology-dependent form for a targeted device. In addition to mapping quantum gates into the supported gate set, it is necessary to map pseudo qubits in the technology-independent circuit into physical qubits of the technology-dependent circuit such that coupling constraints among qubits acting in multiple-qubit gates are satisfied. It is usually not possible to find such a mapping without adding SWAP gates into the circuit. To cope with the technical limitations of NISQ-era quantum devices, it is advantageous to find a mapping that requires as few additional gates as possible. The large search space of possible mappings makes this task a difficult combinatorial optimization problem. In this work, we demonstrate how zero-suppressed decision diagrams (ZDDs) can be used for typical implementation tasks in quantum mapping algorithms. We show how to maximally partition a quantum circuit into blocks of adjacent gates, and if adjacent gates within a circuit do not share common mapping permutations, we attempt to combine them using parallelized SWAP operations represented in a ZDD. Boundaries for the partitions are formed where adjacent gates are unable to be combined. Within each partition block, ZDDs represent all possible mappings of pseudo qubits to physical qubits.

Nested genetic algorithm for highly reliable and efficient embedded system design

Modern embedded systems must have high reliability and performance. They should be able to tolerate both hard as well as soft errors occurring in the resources constituting the system. Reliability must be part of the system design and the system must consist of non expensive off-the-shelf resources. A system-level design process of reliable system demands efficient reliability evaluation of the explored design alternatives (DA). This work presents a new approach to accelerate the calculation of reliability and execution time of the system and thereby suggests the design space exploration for a reliable system. A new data structure denoted as system error decision diagram (SEDD) is proposed, which is based on both binary decision diagrams to model hard errors and zero-suppressed decision diagrams to model soft errors. The construction of the SEDD diagram and the calculation of reliability and execution time are explained in an algorithmic way. SEDD is found to be better in terms of memory requirements and construction time compared to other models available in the literature. Using SEDD and the corresponding algorithms, a nested genetic algorithm is constructed that designs system for lifetime reliability and execution time. The result of the design space exploration algorithm is a set of Pareto DAs. A so-called ‘human designer’ is thus able to select one of the best alternative that represents the given system requirements. The nested genetic algorithm and its benefits are illustrated using a real-life embedded application from automotive domain.

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams ZBDDs. Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram BDD. A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing.

Applications of Zero-Suppressed Decision Diagrams

A zero-suppressed decision diagram (ZDD) is a data structure to represent objects that typically contain many zeros. Applications include combinatorial problems, such as graphs, circuits, faults, and

Partially-shared zero-suppressed multi-terminal BDDs: concept, algorithms and applications

Multi-Terminal Binary Decision Diagrams (MTBDDs) are a well accepted technique for the state graph (SG) based quantitative analysis of large and complex systems specified by means of high-level model description techniques. However, this type of Decision Diagram (DD) is not always the best choice, since finite functions with small satisfaction sets, and where the fulfilling assignments possess many 0-assigned positions, may yield relatively large MTBDD based representations. Therefore, this article introduces zero-suppressed MTBDDs and proves that they are canonical representations of multi-valued functions on finite input sets. For manipulating DDs of this new type, possibly defined over different sets of function variables, the concept of partially-shared zero-suppressed MTBDDs and respective algorithms are developed. The efficiency of this new approach is demonstrated by comparing it to the well-known standard type of MTBDDs, where both types of DDs have been implemented by us within the C++-based DD-package JINC. The benchmarking takes place in the context of Markovian analysis and probabilistic model checking of systems. In total, the presented work extends existing approaches, since it not only allows one to directly employ (multi-terminal) zero-suppressed DDs in the field of quantitative verification, but also clearly demonstrates their efficiency.