Zero Crossing Digital Phase Locked Loop Research Articles

Fixed Point Iteration Chaos Controlled ZCDPLL

The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.

FIR digital filter-based ZCDPLL for carrier recovery

The objective of this work is to analyse the performance of the newly proposed two-tap FIR digital filter-based first-order zero-crossing digital phase-locked loop (ZCDPLL) in the absence or presence of additive white Gaussian noise (AWGN). The introduction of the two-tap FIR digital filter widens the lock range of a ZCDPLL and improves the loop’s operation in the presence of AWGN. The FIR digital filter tap coefficients affect the loop convergence behaviour and appropriate selection of those gains should be taken into consideration. The new proposed loop has wider locking range and faster acquisition time and reduces the phase error variations in the presence of noise.

True Random Bit Generator Using ZCDPLL Based on TMS320C6416

A True Random Binary Generator (TRBG) based on a zero crossing digital phase-locked loop (ZCDPLL) is proposed. In order to face the challenges of using the proposed TRBG in cryptography, the proposed TRBG is subjected to the AIS 31 test suite. The ZCDPLL operate as chaotic generator for certain loop filter gains and this has been used to generate TRBs. The generated binary sequences have a good autocorrelation and cross-correlation properties as seen from the simulation results. A prototype of TRBG using ZCDPLL has been developed through Texas Instruments TMS320C6416 DSP development kit. The proposed TRBG successfully passed the AIS 31 test suit.

Chaos Controlled ZCDPLL for Carrier Recovery in Noisy Channels

The objective of this work is to analyze the performance of the chaos controlled first order Zero Crossing Digital Phase Locked Loop (ZCDPLL) in the presence of Additive White Gaussian Noise (AWGN). The nonlinear behaviour of ZCDPLL shows a period doubling to its route to chaos. The amount of ZCDPLL divergency is measured and fed-back in a form of linear stabilization. The introduction of the chaos control widens the lock range of a ZCDPLL and improves the loop's operation in the presence of AWGN.

Chaos and bifurcation in a third-order digital phase-locked loop

Nonlinear dynamics of a third-order zero crossing digital phase locked loop (ZCDPLL) has been investigated. It has been observed that, while first and second-order ZCDPLLs show period doubling route to chaos, a third-order ZCDPLL manifests a disjoint periodic attractor in its route to chaos. Also, the complexity and predictability of the system dynamics have been characterized by using nonlinear dynamical measures such as Lyapunov exponent, Kaplan–York dimension, correlation dimension and Kolmogorov entropy. All the results show that the chaos in a third-order ZCDPLL is low dimensional.

Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent.

Zero-crossing DPLL bit synchronizer with pattern jitter compensation

A digital phase-locked loop (DPLL) bit synchronizer that tracks the zero crossings of a bandlimited binary signal is discussed. The synchronizer reduces pattern jitter or self noise with a compensation signal in the synchronizer feedback loop without using a prefilter. Analytical results are derived for the timing jitter variance (additive noise and self noise) of the synchronizer. Computer simulations and laboratory measurements are shown to verify the effectiveness of the pattern jitter compensation techinque for a synchronizer operating with both spectral raised cosine signaling pulses as well as for signaling pulses generated by a realizable filter network. Implementation of the pattern jitter compensation method in an adaptive synchronizer structure for applications where a priori knowledge of the signaling pulse shape is not available is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>