Semiconductor Manufacturing Yield Research Articles

A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

PurposeThe purpose of this paper is to identify the root cause of low yield problems in the semiconductor manufacturing process using sensor data continuously collected from manufacturing equipment and describe the process environment in the equipment.Design/methodology/approachThis paper proposes a sensor data mining process based on the sequential modeling of random forests for low yield diagnosis. The process consists of sequential steps: problem definition, data preparation, excursion time and critical sensor identification, data visualization and root cause identification.FindingsA case study is conducted using real-world data collected from a semiconductor manufacturer in South Korea to demonstrate the effectiveness of the diagnosis process. The proposed model successfully identified the excursion time and critical sensors previously identified by domain engineers using costly manual examination.Originality/valueThe proposed procedure helps domain engineers narrow down the excursion time and critical sensors from the massive sensor data. The procedure's outcome is highly interpretable, informative and easy to visualize.

An Improved XGBoost Prediction Model for Multi-Batch Wafer Yield in Semiconductor Manufacturing

Wafer yield is one of the most critical indicators of product quality in semiconductor manufacturing companies. An accurate prediction can reduce the subsequent inspection process, improve production efficiency and reduce product scrap. However, existing end-to-end data-driven wafer yield prediction methods ignore the batch nature of the wafer production process, resulting in poor generalization of the prediction model in different batch wafers. Therefore, an improved XGBoost-based multi-batch wafer yield prediction model is proposed to address this problem. A multi-task learning mechanism is designed to realize the extraction of batch features, and a fusion training mechanism is established to realize the prediction output. Finally, the effectiveness of the prediction method is verified by experimental data collected from the real wafer fabrication process.

Using Bayesian network technology to predict the semiconductor manufacturing yield rate in IoT

In the era of the knowledge economy, one of the key issues is how to integrate and use intelligent information systems to collect data and make valuable predictions to support business decisions. Intelligent information systems use artificial intelligence to enhance system performance, giving the enterprise a competitive advantage. This paper uses ontology technology for user requirements analysis—defining the class, slot, and instance of the ontology—and then designs the system architecture based on that ontology. In accordance with the firm’s requirements, we build a data warehouse system that is integrated with different data sources within the enterprise and that supports a web-based interface in the Internet of Things (IoT). The system also supports the standard queries, reports, summary tables, and datasets required for data mining. The proposed data mining method for manufacturing industries that use Bayesian network incorporates Bayesian theory and graphical models and can predict causal and probabilistic relationships among a set of variables. Our results bring information system functionality closer to satisfying the real-world needs of business. The proposed system can reduce production cycle times, increase the speed and accuracy with which production information is analyzed, and offer predictions that can be used for better business decisions. Data mining technology can improve the efficiency of manufacturing processes by using feedback data to tune the manufacturing parameters and improve the accuracy of yield rate predictions, giving the firm a greater competitive advantage.

Effect of a Trap Zone in Reducing Nanoparticle Contamination of Wafers and Photomasks in Parallel Airflowp

Particle contamination control is important for increasing the yield in semiconductor manufacturing. In this paper, a trap zone was suggested to reduce the level of particulate contamination of wafers and photomasks during transport in horizontal direction. Trap zone efficiency was numerically and theoretically analyzed by calculating local deposition velocity onto a critical surface representing a wafer or a photomask. The effects of diffusion, gravitational settling, convection, and thermophoresis on particle behavior were considered. The deposition velocity onto the critical surface was found to be effectively reduced with the use of the trap zone, especially for nanoparticles of large diffusivity. As the trap zone became longer, the degree of critical surface contamination by nanoparticles was estimated to be more reduced. An equation was suggested to estimate the reduction of particulate contamination of the critical surface as a function of the trap zone length. It is anticipated that the results of this paper are very helpful for designing wafer/photomask transport systems with a reduced level of contamination by nanoparticles.

Clustering Ensemble for Identifying Defective Wafer Bin Map in Semiconductor Manufacturing

Wafer bin map (WBM) represents specific defect pattern that provides information for diagnosing root causes of low yield in semiconductor manufacturing. In practice, most semiconductor engineers use subjective and time-consuming eyeball analysis to assess WBM patterns. Given shrinking feature sizes and increasing wafer sizes, various types of WBMs occur; thus, relying on human vision to judge defect patterns is complex, inconsistent, and unreliable. In this study, a clustering ensemble approach is proposed to bridge the gap, facilitating WBM pattern extraction and assisting engineer to recognize systematic defect patterns efficiently. The clustering ensemble approach not only generates diverse clusters in data space, but also integrates them in label space. First, the mountain function is used to transform data by using pattern density. Subsequently,k-means and particle swarm optimization (PSO) clustering algorithms are used to generate diversity partitions and various label results. Finally, the adaptive response theory (ART) neural network is used to attain consensus partitions and integration. An experiment was conducted to evaluate the effectiveness of proposed WBMs clustering ensemble approach. Several criterions in terms of sum of squared error, precision, recall, andF-measure were used for evaluating clustering results. The numerical results showed that the proposed approach outperforms the other individual clustering algorithm.

A virtual metrology approach for maintenance compensation to improve yield in semiconductor manufacturing

AbstractProcess condition was changed by preventative maintenance that may lead to the inconsistency of process output. In practice, process engineers have difficulties to discover the inconsistency that the defect wafer may have been produced before the next measurement. This study proposes a virtual metrology (VM) approach for maintenance compensation in semiconductor manufacturing. The tool process parameter streams were collected to predict the product metrology value, and a relation model was built to adjust the equipment settings for product recipe compensation. An empirical study in maintenance compensation of chemical vapor deposition (CVD) was conducted in a Taiwan semiconductor company for validation. The thickness difference caused by maintenance was reduced from 571A to 77A in training data and 564A to 210A in testing data. The results showed practical viability of the proposed approach and an intelligent system embedded with the developed algorithm has been implemented.

LCD brightness decay due to particulate contamination of back light unit

So far, particulate contamination problems occurring in cleanroom environments have been intensively investigated by considering the product yield in semiconductor manufacturing or liquid crystal display (LCD) manufacturing. This study, however, focused on the particulate contamination problem causing the degradation of LCD TVs run in common environments. A field test was conducted by running a LCD TV in an office room for 60 days in order to collect and analyze the particles contaminating the backlight unit (BLU) of the LCD TV. Based on the field test result, soot particles were generated to simulate the contaminant particles, and an accelerated test was performed by exposing the LCD TV to a soot aerosol of relatively high concentration. As the exposure time was increased, the degree of particulate contamination of the BLU became more severe, and the decay rate of the LCD brightness increased. As a result, the particulate contamination of the BLU was found to greatly affect the decay rate of the LCD brightness. A numerical simulation was performed to elucidate the mechanism of particle influx into the BLU and to predict the particle deposition pattern. The contaminant particles could enter into the BLU through the gaps on the BLU casing due to the air flow induced by natural convection in the BLU. The particles were thought to have been deposited on the walls in the BLU, especially at the corner regions.

Particle Deposition Velocity onto a Wafer or a Photomask in a Laminar Parallel Flow

Particulate contamination is one of the critical problems that decrease product yield in semiconductor manufacturing. It is therefore important to quickly and correctly predict the particle deposition velocity for controlling the level of particulate contamination. Gaussian diffusion sphere model (GDSM) was employed to predict the mean mass transfer coefficient over a flat plate in a laminar parallel flow. The GDSM was validated for the one-dimensional flat plate by comparing with the laminar boundary layer theory in wide ranges of Schmidt number and fluid temperature. The GDSM was then used to predict the mean mass transfer coefficient over finite flat plates of common areal shapes, i.e., square, rectangle, circle, ellipse, and rhombus, with various aspect ratios. From the GDSM results, the mean Sherwood number correlation was suggested in the form of . The correlation constant was determined as for square/rectangular flat plates, for circular/elliptical flat plates, and for rhombic flat plates. The applicable Reynolds number range of the correlation was proposed by comparing with the simulation data. Finally, the equation to predict the particle deposition velocity onto a wafer or a photomask surface exposed to a parallel flow was suggested.

Impact of Metal-Ion Contaminated Silica Particles on Gate Oxide Integrity

The impact of metal-ion contamination (present on wafer surface before oxidation) on gate oxide integrity (GOI) is well known in literature, which is not the case for clean silica particles [1, 2]. However, it is known that particles present in ultra-pure water (UPW) decrease the random yield in semiconductor manufacturing [3]. The presence of silica in UPW is common knowledge. UPW has also a certain content of metal ions, which can be attached to silica. That means, when a wafer is in contact with UPW metal ion can directly and/or in form of a silica-metal conglomerate be attached to the wafer surface. That means, it is not known in which form metal-ion contamination will deteriorate GOI the most. In order to receive more clarity in this field a short-loop study was set up, where we want distinguish between the impacts of - low metal ion contamination (Calcium), - clean silica particles (330nm) contamination, - silica particles with metal-ion core (330nm) contamination, and - metal-ion contamination at similar concentration as the metal-ion core of the particles on GOI (uniform and none uniform distribution).

Modeling and Forecasting of Defect-Limited Yield in Semiconductor Manufacturing

A detailed cause-and-effect stochastic model is developed to relate the type, size, location, and frequency of observed defects to the final yield in IC manufacturing. The model is estimated on real data sets with a large portion of unclassified defects and un inspected layers, and in presence of clustering of defects. Results of this analysis are used for evaluating kill ratios and effects of different factors, identifying the most dangerous cases and the most probable causes of failures, forecasting the yield, and designing optimal yield-enhancement strategies.

Measurement Techniques of Sheet Resistance on Copper Defects after Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) has been widely used in removing overburden copper (Cu) interconnects to realize global plannariztion. However, Cu defects including void, dishing, and erosion etc. always accompany after CMP process to influence semiconductor manufacturing yield. In this study, an accurate measurement technique of sheet resistance on erosion defect after Cu CMP is investigated by estimating Cu metal line resistance and applying some mathematic equations to calculate the thickness of erosion defect. By way of the results, the accuracy of this measurement model of erosion defect is high and the error is smaller than 100 Å. In addition, it is also suitable for exploring different wafer conditions such as Cu metal line widths and pattern densities, even process recipe. Therefore, this novel method benefits greatly on monitoring in-situ the degree of erosion defect after CMP to avoid a large number yields coming down.

Using expert technology to select unstable slicing machine to control wafer slicing quality via fuzzy AHP

Silicon wafer slicing is an increasingly complex manufacturing process. This involves high purity levels, crystallographic perfection and precise mechanical tolerances, thus 12 in. wafer slicing is the most difficult in terms of semiconductor manufacturing yield. As silicon wafer slicing directly impacts production costs, semiconductor manufacturers are especially concerned with increasing and maintaining the yield, as well as identifying why yields decline. The criteria for establishing the proposed algorithm are derived from literature review and modified Delphi method in semiconductor manufacturing. The main objective of this paper is to propose a new approach within the AHP framework for tackling the uncertainty and imprecision of silicon wafer slicing evaluations during manufacturing process stages, where the decision-maker’s comparison judgments are represented as fuzzy triangular numbers. Additionally, the proposed algorithm can select the evaluation outcomes to identify the worst machine of precision. Finally, results of EWMA control chart demonstrate the feasibility of the proposed fuzzy AHP-based algorithm in effectively selecting the evaluation outcomes and evaluating the precision of the worst performing machines. So, through collect data (the quality and quantity) to judge the result by fuzzy AHP, it will the key to help the engineer can find out the manufacturing process yield quickly effectively.

Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing

Semiconductor manufacturing involves lengthy and complex processes, and hence is capital intensive. Companies compete with each other by continuously employing new technologies, increasing yield, and reducing costs. Yield improvement is increasingly important as advanced fabrication technologies are complicated and interrelated. In particular, wafer bin maps (WBM) that present specific failure patterns provide crucial information to track the process problems in semiconductor manufacturing, yet most fabrication facility (fabs) rely on experienced engineers’ judgments of the map patterns through eye-ball analysis. Thus, existing studies are subjective, time consuming, and are also restricted by the capability of human recognition. This study proposes a hybrid data mining approach that integrates spatial statistics and adaptive resonance theory neural networks to quickly extract patterns from WBM and associate with manufacturing defects. An empirical study of WBM clustering was conducted in a fab for validation. The results showed practical viability of the proposed approach and now an expert system embedded with the developed algorithm has been implemented in a fab in Taiwan. This study concludes with a discussion on further research.

Evaluating and controlling silicon wafer slicing quality using fuzzy analytical hierarchy and sensitivity analysis

Twelve-inch wafer slicing is the most challenging process in semiconductor manufacturing yield. This study applies the fuzzy analytic hierarchy process (FAHP) not only to construct the multi-criteria decision problem and determine criteria weights, but also to assess the expected contributions of alternatives to previously defined objectives. Therefore, the fuzzy AHP-based proposed algorithm is applied to select evaluation outcomes and evaluate the precision of optimal performing machines. Additionally, a case study and the exponential weighted moving average (EWMA) control chart are presented to demonstrate and verify the feasibility and effectiveness of the proposed method. Finally, sensitivity analysis is conducted to test the stability of the priority ranking and help online engineers understand multi-criteria decision scenarios that reflect alternative future developments or different perspectives regarding the relative importance of the criteria.

Online Experts Screening the Worst Slicing Machine to Control Wafer Yield via the Analytic Hierarchy Process

This study describes a novel algorithm for optimizing the quality yield of silicon wafer slicing. 12 inch wafer slicing is the most difficult in terms of semiconductor manufacturing yield. As silicon wafer slicing directly impacts production costs, semiconductor manufacturers are especially concerned with increasing and maintaining the yield, as well as identifying whey yeilds decline. The criteria for establishing the proposed algorithm are derived from a literature review and interviews with a group of experts in semiconductor manufacturing. The modified Delphi method is then adopted to analyze those results. The proposed algorithm also incorporates the analytic hierarchy process (AHP) to determine the weights of evaluation. Additionally, the proposed algorithm can select the evaluation outcomes to identify the worst machine of precision. Finally, results of the exponential weighted moving average (EWMA) control chart demonstrate the feasibility of the proposed AHP‐based algorithm in effectively selecting the evaluation outcomes and evaluating the precision of the worst performing machines. So, through collect data (the quality and quantity) to judge the result by AHP, it is the key to help the engineer can find out the manufacturing process yield quickly effectively.

Data Mining using Genetic Programming for Construction of a Semiconductor Manufacturing Yield Rate Prediction System

The complexity of semiconductor manufacturing is increasing due to the smaller feature sizes, greater number of layers, and existing process reentry characteristics. As a result, it is difficult to manage and clarify responsibility for low yields in specific products. This paper presents a comprehensive data mining method for predicting and classifying the product yields in semiconductor manufacturing processes. A genetic programming (GP) approach, capable of constructing a yield prediction system and performing automatic discovery of the significant factors that might cause low yield, is presented. Comparison with the results then is performed using a decision tree induction algorithm. Moreover, this research illustrates the robustness and effectiveness of this method using a well-known DRAM fab’s real data set, with discussion of the results.

Run-to-Run Overlay Control of Steppers in Semiconductor Manufacturing Systems Based on History Data Analysis and Neural Network Modeling

This paper presents a new run-to-run control scheme to reduce overlay misalignment errors in steppers and demonstrates the feasibility of the scheme by real-time experimental tests. The overlay misalignment error mainly depends on two factors: one is the internal dynamics of photo processes and steppers and the other is the process history of lots, such as base equipment and reticles. Based on these observations, a new control scheme was designed to find the stepper inputs minimizing the misalignment errors based on history data analysis and neural network models. Moreover, we demonstrated that the proposed control scheme reduces the spec-out ratios as well as the number of engagements of the send-ahead wafer process, which thereby results in the increase of product yield in semiconductor manufacturing.

Dishing-Radius Model of Copper CMP Dishing Effects

Copper chemical-mechanical polishing (CMP) dishing concerns semiconductor manufacturing yield in contemporary back-end-of-the-line process. In this work, we first propose and validate a dishing model through first-principle analysis and carefully designed experimentation. This model utilizes the novel concept of dishing radius, a metric that assumes cylindrically shaped post-CMP copper surface and directly captures the extent of metal dishing for a CMP process. Additionally, a dishing-model-based method for extracting the parameterized two-dimensional post-CMP metal profile is developed for damascene structures. The case study utilizing this method shows that the extracted parameters are in good agreement with those from cross-sectional scanning electron microscopy and surface profilers, which confirmed that dishing radius is linewidth-independent for typical metal lines. This method is particularly useful in determining dishing artifacts, which are modeled using the dishing radius concept. The approach is nondestructive, precise, and efficient.

Kinetic Limitations on Metal Dissolution during Aqueous Silicon Wafer Processing

Metal contamination during aqueous processing has recently been a subject of great interest,1-14 since metal surface contamination can decrease yield in semiconductor manufacturing by causing a wide variety of electrical problems.1,3,5,6 For example, the metal contamination tolerance level for 16 megabyte (MB) dynamic random access memory (DRAM) devices is approximately 1010 metal atoms/cm2.15-17 Deposition has been suggested to occur by a variety of mechanisms,4,6,16,18 including precipitation from a supersaturated cleaning solution and incorporation into the silicon dioxide layer during oxide regrowth. The most problematic is a proposed electroless process whereby metal ion reduction and silicon oxidation occur simultaneously following HF dissolution of the native oxide.4 The physical processes which occur during dissolution and removal have been less studied, although they can also be important to obtaining a contamination-free substrate. For example, during Cu dissolution into an SC-1 process solution, one might expect the electroless dissolution in this basic solution to occur via the following half-reactions

The yield models and defect density monitors for integrated circuit diagnosis

In IC manufacturing, the yield of a product is of important consideration. The yield of a circuit is governed by the defects developed in the circuit during fabrication. The accurate identification of the fault and its location helps in improving yield and in reducing development time. This paper reviews the yield models used in predicting the IC yield in semiconductor manufacturing and discusses the practical approach to yield analysis. An approach to systematic process diagnosis by IC structural decomposition is discussed. The design method and layout of some of the defect density test structure monitors are discussed. An example of the process problem analysis is also given.