Yield-aware Optimization Research Articles

PoBO: A Polynomial Bounding Method for Chance-Constrained Yield-Aware Optimization of Photonic ICs

Conventional yield optimization algorithms try to maximize the success rate of a circuit under process variations. These methods often obtain a high yield but reach a design performance that is far from the optimal value. This article investigates an alternative yield-aware optimization for photonic ICs: we will optimize the circuit design performance while ensuring a high yield requirement. This problem was recently formulated as a chance-constrained optimization, and the chance constraint was converted to a stronger constraint with statistical moments. Such a conversion reduces the feasible set and sometimes leads to an over-conservative design. To address this fundamental challenge, this article proposes a carefully designed polynomial function, called optimal polynomial kinship function, to bound the chance constraint more accurately. We modify existing kinship functions via relaxing the independence and convexity requirements, which fits our more general uncertainty modeling and tightens the bounding functions. The proposed method enables a global optimum search for the design variables via polynomial optimization. We validate this method with a synthetic function and two photonic IC design benchmarks, showing that our method can obtain better design performance while meeting a prespecified yield requirement. Many other advanced problems of yield-aware optimization and more general safety-critical design/control can be solved based on this work in the future.

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.

Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies

This paper proposes a novel yield-aware optimization methodology that can be used for mixed-domain synthesis of robust micro-electro-mechanical systems (MEMS). The robust Pareto front optimization of a MEMS accelerometer system, which includes a capacitive MEMS sensor and an analog read-out circuitry, is realized by co-optimization of the mixed-domain system where the sensor performances are evaluated using highly accurate analytical models and the circuit level simulations are carried out by an electrical simulator. Two different approaches for yield-aware optimization have been implemented in the synthesis loop. The Quasi Monte Carlo (QMC) technique has been used to embed the variation effects into the optimization loop. The results for both two- and three-dimensional yield-aware optimization are quite promising for robust MEMS accelerometer synthesis.

Chance-Constrained and Yield-Aware Optimization of Photonic ICs With Non-Gaussian Correlated Process Variations

Uncertainty quantification has become an efficient tool for uncertainty-aware prediction, but its power in yield-aware optimization has not been well explored from either theoretical or application perspectives. Yield optimization is a much more challenging task. On one side, optimizing the generally non-convex probability measure of performance metrics is difficult. On the other side, evaluating the probability measure in each optimization iteration requires massive simulation data, especially when the process variations are non-Gaussian correlated. This paper proposes a data-efficient framework for the yield-aware optimization of photonic ICs. This framework optimizes the design performance with a yield guarantee, and it consists of two modules: a modeling module that builds stochastic surrogate models for design objectives and chance constraints with a few simulation samples, and a novel yield optimization module that handles probabilistic objectives and chance constraints in an efficient deterministic way. This deterministic treatment avoids repeatedly evaluating probability measures at each iteration, thus it only requires a few simulations in the whole optimization flow. We validate the accuracy and efficiency of the whole framework by a synthetic example and two photonic ICs. Our optimization method can achieve more than $30\times$ reduction of simulation cost and better design performance on the test cases compared with a Bayesian yield optimization approach developed recently.

Multi-objective optimization and analysis for the design space exploration of analog circuits and solar cells

This paper introduces PareDA (ParetoDesignAutomation), a composite automated methodology for the optimization of analog circuits and solar cell devices. The PareDA framework combines randomized algorithms, domain and constraints sensitivity analysis, epsilon-dominance and global robustness analysis in order to perform simulation-based, multi-scenario and multi-objective optimization. PareDA is evaluated on the problems of designing a three-stage operational amplifier, a yield-aware optimization of a folded-cascode operational amplifier (requiring multiple operating conditions) and a model for selective emitter solar cells.Comparisons with a selection of state-of-the-art techniques (such as NSGA-II and YdIRCO) highlight the effectiveness of PareDA both in terms of Pareto optimality of the solutions found and time-to-converge. The solutions obtained by PareDA dominate those of comparative techniques, in particular, the proposed technique shows a significant average performance improvement (ranging from 35% to 49%) with respect to such techniques. Moreover, the CPU time required by PareDA to converge is smaller of at least 75% if compared with the other methodologies here analyzed (e.g. significantly improved designs for folded-cascode operational amplifier are found in just 320s). Finally, the PareDA algorithm can also benefit from parallelization, which leads to a significant speed-up with respect to the nonparallel version.

Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning

A hierarchical optimization methodology is presented to achieve robust analog/mixed-signal circuit design with consideration of process variations. Hierarchical optimization using building circuit block Pareto models is an efficient approach for optimizing nominal performances of large analog circuits. However, yield-aware system optimization, as dictated by the need for safeguarding chip manufacturability in scaled technologies, is completely nontrivial. Two fundamental difficulties are addressed for achieving such a methodology: yield-aware Pareto performance characterization at the building block level and yield-aware optimization problem formulation at the system level. In addition, postsilicon tuning in complex mixed-signal system designs is investigated and the proposed optimization framework is extended for such systems. The presented methodology is demonstrated by hierarchical optimization of a phased-locked loop consisting of multiple building blocks and self-tuning function blocks.