Xilinx Virtex-II Pro FPGA Research Articles

High Performance and Reliable Fault Detection Scheme for the Secure Hash Algorithm

Background/Objectives: Among the powerful techniques against the protected hash functions (SHA) the method of fault injection attacks. For obtain the confidential information, the method consist to inject this attacks during the process of the hash algorithm. In literature, they proposed a many methods of countermeasures to secure the SHA implementation against these attacks. Methods/Statistical Analysis: In this paper, we proposed a new scheme of fault detection; this scheme is based on the combines of two redundancies named hybrid redundancy for the hash algorithm. The weaknesses and the strengths of our proposed method against the fault attacks are discussed. Findings: our schemes proposed reaches 99.999% fault coverage. Moreover, we are implemented our proposed scheme on Xilinx Virtex-5 and Virtex-II Pro FPGA. Its area overhead fault coverage, frequency and throughput degradation have been compared and it is shown that our proposed scheme allows a trade-off between the security of the SHA and hardware overhead. Application/Improvements: Compared to other work, our fault detection scheme has the important performances in terms of frequency, occupied slices, fault coverage and throughput.

Scalable hardware architecture for disparity map computation and object location in real-time

We present the disparity map computation core of a hardware system for isolating foreground objects in stereoscopic video streams. The operation is based on the computation of dense disparity maps using block-matching algorithms and two well-known metrics: sum of absolute differences and Census transform. Two sets of disparity maps are computed by taking each of the images as reference so that a consistency check can be performed to identify occluded pixels and eliminate spurious foreground pixels. Taking advantage of parallelism, the proposed architecture is highly scalable and provides numerous degrees of adjustment to different application needs, performance levels and resource usage. A version of the system for 640 × 480 images and a maximum disparity of 135 pixels was implemented in a system based on a Xilinx Virtex II-Pro FPGA and two cameras with a frame rate of 25 fps (less than the maximum supported frame rate of 40 fps on this platform). Implementation of the same system on a Virtex-5 FPGA is estimated to achieve 80 fps, while a version with increased parallelism is estimated to run at 140 fps (which corresponds to the calculation of more than 5.9 × 109 disparity-pixels per second).

An Implementation of High-speed Serial Transmission by RocketIO Used on SAR System

Synthetic Aperture Radar is an efficient method of remote sensing.In the real-time processing system of Synthetic Aperture Radar,the high-speed data transmission is the emphases and the difficulty all the while.Aiming at the RocketIO Tranceiver module of Xilinx Virtex-Ⅱ PRO FPGA,This paper designs a high-speed serial I/O PCB board used on SAR data transmission system.This board uses RocketIO module in the chip fully,BREFCLK differential input reference clock,8B/10B decoder and pre-emphasis technology etc;implements one RocketIO transmission at 3.125 Gb/s and multi-channel high-speed serial interconnection.It is reliable through validated by actual system.The results of simulation and experimentation on the hardware circuit prove this method is efficient.and can reduce the design's complexity and board size very well.

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4:2:2 profile

This article presents the HP422-MoCHA: optimized Motion Compensation hardware architecture for the High 4:2:2 profile of H.264/AVC video coding standard. The proposed design focuses on real-time decoding for HDTV 1080p (1,920 × 1,080 pixels) at 30 fps. It supports multiple sample bit-width (8, 9, or 10 bits) and multiple chroma sub-sampling formats (4:0:0, 4:2:0, and 4:2:2) to provide enhanced video quality experience. The architecture includes an optimized sample interpolator that processes luma and chroma samples in two parallel datapaths and features quarter sample accuracy, bi-prediction and weighted prediction. HP422-MoCHA also includes a hardwired Motion Vector Predictor, supporting temporal and spatial direct predictions. A novel memory hierarchy implemented as a 3-D Cache reduces the frame memory access, providing, on average, 62% of bandwidth and 80% of clock cycles reduction. The design was implemented in a Xilinx Virtex-II PRO FPGA, and also in an ASIC with a TSMC 0.18 μm standard cells technology. The ASIC implementation occupies 102 K equivalent gates and 56.5 KB of on-chip SRAM in a 3.8 × 3.4 mm2 area. It presents a power consumption of 130 mW. Both implementations reach a maximum operation frequency of ~100 MHz, being able to motion compensate 37 bi-predictive frames or 69 predictive fps. The minimum required frequency to ensure the real-time decoding for HD1080p at 30 fps is 82 MHz. Since HP422-MoCHA is the first Motion Compensation architecture for the High 4:2:2 profile found in the literature, a Main profile MoCHA was used for comparison purposes, showing the highest throughput among all presented works. However, the HP422-MoCHA architecture also reaches the highest throughput when compared with the other published Main profile MC solutions, even considering the significantly higher complexity of the High 4:2:2 profile.

Easy-hardware-implementation MMPF for Maneuvering Target Tracking: Algorithm and Architecture

In this paper, we present an easy-hardware-implementation multiple model particle filter (MMPF) for maneuvering target tracking. In the proposed filter, the sampling importance resampling (SIR) filter typically used for nonlinear and/or non-Gaussian application is extended to incorporating multiple models that are composed of a constant velocity (CV) model and a "current" statistical (CS) model, and the Independent Metropolis Hasting (IMH) sampler is utilized for the resampling unit in each model. Compared with the bootstrap MMPF, the proposed MMPF requires no knowledge of models and model transition probabilities for different maneuvering motions, and keeps a constant number of particles per model at all times. This allows a regular pipelined hardware structure and can be implemented in hardware easily. Furthermore, using the IMH sampler for the resampling unit avoids the bottleneck introduced by the traditional systematic resampler and reduces the latency of the whole implementation. Simulation results indicate that the proposed filter has approximately equal tracking performance with the bootstrap MMPF. Hardware architecture of the IMH sampler and its corresponding sample unit are presented, and a parallel architecture consisting of CV model processing element (PE), CS model PE and a central unit (CU) is described. The proposed architecture is evaluated on a Xilinx Virtex-II Pro FPGA platform for a maneuvering target tracking application and the results show many advantages of the proposed MMPF over existing approaches in terms of efficiency, lower latency, and easy hardware implementation.

Design and implementation of a MicroBlaze-based warp processor

While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed technology of warp processing can help reduce those penalties. Warp processing is the dynamic and transparent transformation of critical software regions from microprocessor execution to much faster circuit execution on an FPGA. In this article, we describe an implementation of a warp processor on a Xilinx Virtex-II Pro and Spartan3 FPGAs incorporating one or more MicroBlaze soft processor cores. We further provide a detailed analysis of the energy overhead of dynamically partitioning an application's kernels to hardware executing within an FPGA. Considering an implementation that periodically partitions the executing application once every minute, a MicroBlaze-based warp processor implemented on a Spartan3 FPGA achieves average speedups of 5.8× and energy reductions of 49% compared to the MicroBlaze soft processor core alone—providing competitive performance and energy consumption compared to existing hard processor cores.

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memory blocks between all half-iterations to be removed is presented. A complexity analysis of the elementary decoder leads to a low complexity decoder architecture for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup which also includes an innovative parallel product encoder. The implemented block turbo decoder processes input data at 600 Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Some solutions to reach even higher data rates are finally presented.

Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs

This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played only when the downloaded circuit is correctly combined (= interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. This paper describes the detailed architecture of the system and clarify the feasibility and effectiveness of the system. In addition, we discuss a fail-safe mechanism and future work necessary for the practical application of the system.

Fast Chirplet Transform With FPGA-Based Implementation

This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

FPGA based string matching for network processing applications

String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming and cannot meet gigabit bandwidth requirements. Implementing this process in hardware improves the search time considerably and has several other advantages. This paper presents an array based hardware implementation of this time consuming process for network intrusion detection and directory lookup applications using reconfigurable hardware. These designs are coded in VHDL targeting a Xilinx Virtex-II Pro FPGA and are evaluated in terms of the speed and resource utilization.

On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC

H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 μm TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro's FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.

A High-End Real-Time Digital Film Processing Reconfigurable Platform

Digital film processing is characterized by a resolution of at least 2 K (2048 × 1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4 K (8.8 Gbit/s) and even 8 K (35.2Gbit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage, and a PCI-Express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: (a) the used design methodology which combines macro component configuration and macrolevel floorplaning with weak programmability using distributed microcoding, (b) the global communication framework with communication scheduling, and (c) the configurable multistream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16 × 16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth, will be shown.

An FPGA- Based General-Purpose Data Acquisition Controller

System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems