Xilinx SDSoC Research Articles

Parallelization and Hardware Mapping of Deep Neural Network on Reconfigurable Platform for AI-Enabled Biomedical System

COVID-19 is still disrupting many parts of the world. A rapid and accurate diagnosis solution is needed to combat the pandemic. As a part of the AIRBiS(AI-Enabled Real-time Pneumonia Detection Bio-medical System), this work conduct hardware acceleration to speed up the diagnosis. We found that more than 90% of the current diagnosis time is spent on the convolution function and have conducted three methods to speed up the convolution operations. Firstly, by applying the Winograd algorithm on convolution layers, the multiplication operations of the matrices can be decreased, which speeds up the calculation. The next step is to improve the data exchange speed between the FPGA and CPU by replacing the normal buffer with LineBuffer. We also tried to improve the calculation speed by quantization, reducing the number of bits used for the filter and the input image. The FPGA board we used for this research is ZCU102. The application used for high-level synthesis is Xilinx SDSoC 2019.1. Using the mentioned approaches, we improved the inference speed from 106ms to 22.2ms per image.

Implementation of deep neural networks on FPGA-CPU platform using Xilinx SDSOC

Deep Convolutional Neural Networks (CNNs) are the state-of-the-art systems for image classification due to their high accuracy but on the other hand their high computational complexity is very costly. The acceleration is the target in this field nowadays for using these systems in real time applications. The Graphics Processing Units is the solution but its high-power consumption prevents its utilization in daily-used equipment moreover the Field Programmable Gate Array (FPGA) has low power consumption and flexible architecture which fits more for CNN implementations. This work discusses this problem and provides a solution that compromises between the speed of the CNN and the power consumption of the FPGA. This solution depends on two main techniques for speeding up: parallelism of layers resources and pipelining inside some layers. On the other hand, we added a new methodology to compromise the area requirements with the speed and design time by implementing CNN using Xilinx SDSOC tool (including processor and FPGA on the same board). Implementing design using HW/SW partitioning will enhance time design based on high level language(C or C++) in Vivado HLS (High Level Synthesis). It also fits for more large designs than using FPGA only and faster in design time.

Efficient co-design partitioning of WLANs on SoC-based SDRs

Software-defined radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with a greater emphasis on programmability, flexibility, portability, and energy efficiency in cellular, WiFi, and M2M communication. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. In this paper, we discuss the HW/SW co-design approach for SDR platforms in the context of wireless communication protocols. We offer a partitioning method of heterogeneous SDR architectures and then discuss the use of Xilinx SDSoC tool for accurate and effective system profiling. To demonstrate our method, we use IEEE 802.11a wireless standard to implement on the Xilinx Zynq-7000 System-on-Chip (SoC). We are able to achieve a significant speedup of 8.7 $$\times$$, compared to a software-only implementation. We also achieved a factor of 1.07 $$\times$$ improvement in terms of power consumption, compared to a hardware-only implementation. Optimization techniques are also adopted for further speedups, and their effectiveness enable us to achieve a speedup of 1.08 $$\times$$, compared to a hardware-only implementation.

Zynq FPGA based and Optimized Design of Points of Interest Detection and Tracking in Moving Images for Mobility System

In this paper, an FPGA based mobile feature detection and tracking solution is proposed for complex video processing systems. Presented algorithms include feature (corner) detection and robust memory allocation solution to track in real-time corners using the extended Kalman filter. Target implementation environment is a Xilinx Zynq SoC FPGA based. Using the HW/SW partitioning flexibility of Zynq, the ARM dual core processor performance and hardware accelerators generated by Xilinx SDSOC and Vivado HLS tools improve the system ability of processing video accurately with a high frame rate. Several original innovations allow to improve the processing time of the whole system (detection and tracking) by 50% as shown in experimental validation (tracking of visually impaired during their outdoor navigation).

A Study of Heterogeneous Computing Design Method based on Virtualization Technology

One challenge for the heterogeneous computing with the FPGA is how to bridge the development gap between SW and HW designs. The high level synthesis (HLS) technique allows producing hardware with high level languages like C. Design tools based on the HLS like Xilinx SDSoC and SDAccel are developed to speedup SW/HW co-designs. However, the developers still require much circuit design skills to use these tools more efficiently. In this paper, we propose a heterogeneous computing platform based on the virtualization technology, namely hCODE.With the help of the virtualization, the HW and SW design can be totally separated. This brings multiple benefits like accelerating a program without modifying or recompiling it, enable high portability and scalability across different HW and operating system.