Xilinx PlanAhead Research Articles

On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm

The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

SummaryThe vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

Area Efficient 64-Point Split Radix FFT using Single-Path Delay Feedback And Multi-Path Delay Commutator (SDF-MDC) Architecture

Fast Fourier Transformation (FFT) is one of the basic operations in field of digital signal and image processing. Signal analysis, Data Compression, Sound Filtering, Partial differential equations, Multiplication of large integers, Image filtering are the important applications of the Fast Fourier Transform. In this paper, pipelined 64-point split radix Single-path Delay Feedback (SDF)-Multi-path Delay Commutator (MDC) FFT has been proposed. With the help of SDF and MDC data flow structures, the proposed FFT architectures are designed. A split radix FFT has lesser counts of adder and multiplication than the mixed radix FFT. These proposed architecture which is used to reduce the slices and LUTs and also increase the speed of the processor. The proposed architecture offers 16.82% reduction in slices, 34.05% reduction in slice registers, 54.67% reduction in flipflops, and 24.69% reduction in slice LUTs, 24.27% reduction in logic, 22.71% reduction in unused flipflops, 35.11% reduction LUT-flipflop pairs, and 60.25% reduction delay than the traditional 64-point mixed radix FFT. Simulation of proposed FFT architectures are done by using Model Sim 6.3C and performances are validated by using Xilinx Plan-ahead Integrated Circuit (IC) vendors.

FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm

Edge detection is a very important area in the field of Computer Vision. Edge detectors behave very poorly, their behavior may fall within tolerance in specific situations and have difficulty in adapting to different situations. Human vision is inherently a multiscale phenomenon and is sensitive to orientation and elongation. This work proposes the hardware implementation of efficient fuzzy logic based algorithm, which is used to detect the edges of an image without determining the threshold value. Edge detection in software is not suited for strong real-time applications. This problem is resolved by using hardware implementation on field programmable gate arrays (FPGAs). Fuzzy inference system is developed with four input pixel containing two fuzzy sets (FSs) one for white and another for black and one output pixel containing three FSs for white, black and edge. Fuzzy if-then rules are used to modify the membership functions. Finally, Mamdanidefuzzifier method is used to form the final edge image. For comparison, the same work was implemented using sobel operator. The hardware part is developed by using Verilog language. The FPGA implementation is targeted on Virtex5 Starter kit (xc5vlx50tff1136-1) and Virtex7 starter kit (xc7vx485tffq1157-1) using the updated Xilinx PlanAhead within the ISE 13.4 development suite. The edge thickness can be changed easily by adding new rules or changing output parameters. That is, rule-based approach has flexible structure that can be easily adapted to any time or anywhere and the new fuzzy approach produces better result than sobel operator. Experimental results show the ability and high performance of the proposed algorithm.

FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique

<p>This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm. For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.</p>

A Novel Design of Low Power, High Speed SAMM and its FPGA Implementation

matrix multiplication is a computationally intensive problem and a prerequisite in various image processing applications like spatial and frequency filtering, edge detection and convolution. Being a core part of various applications in portable devices like mobile phones, demand for high speed and low power consumption is extremely high. This work demonstrates an effective design and efficient implementation of the Matrix Multiplication using Systolic Architecture and Ancient mathematics. For efficient implementation and maximum speed-up, integer arithmetic was used. Three main steps of the work, i.e. design, simulation and implementation, were accomplished. For design and simulation, Verilog HDL was used. The design was simulated using modelsim10.1d and synthesized using Xilinx Planahead 12.1. The work also includes the comparison between three design approaches of the matrix multiplication using systolic architecture. In the first design approach, array multipliers were used. In the second approach, Wallace tree multipliers were used and in the final approach, matrix multiplier design was based on Ancient multiplication technique.