X86 Microprocessors Research Articles

Optimal time-distributed fast Fourier transform: Application to online iterative learning control—experimental high-speed nanopositioning example

In this paper, an optimal time-distributed fast Fourier transform algorithm and a time-distributed inverse fast Fourier transform (OTD-FFT/TD-IFFT) algorithm are proposed. This work is motivated by the need to implement FFT/IFFT online on general microprocessors (e.g., Intel’s x86 microprocessors) in control applications and signal processing, for example, online implementation of frequency domain iterative learning control (FD-ILC) techniques. In these applications, the conventional FFT algorithm executes all the calculations within one single sampling period, thereby, becoming the bottleneck in online implementations of signal processing and control algorithms. In the proposed OTD-FFT technique, the FFT computation of an online sampled data sequence is optimally distributed among all the sampling periods without increasing the total computational complexity, arriving at the minimal per-sampling-period computational complexity. As a result, the entire Fourier transformed sequence is obtained without latency. The proposed approach is extended to online IFFT computation, and then applied to online FD-ILC implementation. The computational complexity analysis shows that by using the proposed approach, the per-sampling-period computational complexity is substantially reduced. The efficacy of the proposed OTD-FFT/TD-FFT for online implementation of FD-ILC technique is demonstrated through experiments of high-speed trajectory tracking on a piezoelectric actuator.

윈도우 기반의 점검장비에 실시간성을 지원하는 실시간 이식 커널의 설계 및 구현

최근 다양한 신무기가 개발됨에 따라 개발된 무기들을 시험하기 위한 점검장비의 실시간성이 필수적으로 요구되고 있다. 하지만 윈도우 기반의 점검장비는 실시간성을 지원하지 못하기 때문에 RTX나 INtime같은 고가의 서드파티 운영체제를 사용함으로써 실시간성을 지원하며, 이는 점검장비 프로그램 개발비용의 증가를 초래하고 있다. 본 논문은 윈도우에 디바이스 드라이버 형태로 이식되어 동작하는 실시간 이식 커널인 RTiK을 제안한다. RTiK은 x86 하드웨어에서 제공하는 Local APIC를 이용하여 윈도우 별도의 타이머를 제공한다. 윈도우 독립적인 타이머 인터럽트의 발생으로 실시간성이 필요한 서비스를 주기적으로 동작시켜주며 마감시한을 보장해줌으로써 윈도우에 실시간성을 제공해준다. 또한 인터럽트 지연시간을 줄이기 위해 윈도우에서 제공하는 지연처리호출(Deferred Procedure Call)을 사용하였으며 지연처리호출에서 실행시켜줄 개발자 정의 함수를 실시간 이식커널 내부에 접근하지 않고 구현 및 수정할 수 있도록 Export Driver를 사용했다. 본 논문에서는 x86하드웨어에서 동작하는 윈도우 기반의 점검장비에 실시간성을 지원하는 실시간 이식커널을 설계 및 구현하고, 0.1ms 주기성 보장에 대해 오실로스코프로 검증한다. Recently, as new weapons are being developed, test equipments to test their functions inevitably require real-time features. However, since test equipments based on Windows can not support real-time requirements, we have no choice but to use third-party solutions such as RTX or INtime. This leads to increase the development cost of each test equipment. This paper suggests an real-time implemented kernel(RTiK) which operates as a device driver on Windows. RTiK provides another timer using the Local APIC of x86 microprocessors. It supports real-time requirements by periodically executing the required services using Windows-independent timer interrupts to guarantee task deadlines. To reduce the interrupt latency, we used deferred procedure calls provided by Windows. We also used the export driver to implement and modify user-defined functions without accessing the RTiK internals. Using an oscilloscope, we prove that the RTiK kernel proposed in this paper guarantees up to 0.1ms periods.

First Silicon Functional Validation and Debug of Multicore Microprocessors

Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency, ordering, and atomicity is crucial. X86 microprocessors are prevalent at most levels of computing. Thus, new x86 microprocessors undergo extensive compatibility testing. Being a high volume product, the economic and logistical repercussions of a functional deficiency escaping into the production cycle and beyond are humbling. The first silicon functional validation and debug of multicore microprocessors are constrained by design complexity, compatibility with existing hardware and software, and time-to-market pressures. This paper describes microprocessor debug features and their use in debugging functional failures. An encompassing overview of the microprocessor's first silicon validation is presented. Emphasis is put on validation and debug of multicore microprocessors targeting multinode systems. This paper presents a novel method to validate and debug intra-node and inter-node communication traffic. This paper also develops an analysis to determine optimal on die debug resources. Finally, data from an 8-node system is presented to demonstrate the extent of intrusiveness of a coherent and noncoherent traffic debug feature

Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors

This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional-unit usage and the microoperation level parallelism (MLP), which together determine the proper functional-unit allocation for superscalar microprocessors, such as the x86 microprocessors. The proposed techniques fit in the early design exploration phase in which the trace or microarchitecture simulator has not been available. The techniques have been applied to analyze several popular Windows95 applications such as Word, Excel, Communicator, etc., for their MLP and distribution of functional-unit usage. The results are used to evaluate the resource allocation of several existing x86 superscalar microprocessors and suggest future extension.