X86 ISA Research Articles

The Challenges of Lecture Delivery of Arm X86, Cisc and Risc in the Teaching of Coursecsc303 (Computer Architecture) in the University of Jos, Nigeria: an Overview

The trending definition of the computer architecture course involves the teaching/delivery of instruction set architecture design, micro architecture design, logic design, and implementation. Historically, the RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape (Patterson D.A & Ditzel D.R, 1980). Today and particularly in developing economies like Nigeria, energy and power pose the primary constraints to architecture design and the computing landscape is significantly different occasioned by growth in tablets and Smartphone's running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISCISA). Furthermore, the traditionally low-power ARM ISA is entering the highperformance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market.ICT has given rise to a host of legal and ethical issues and challenges in the use of ICT for education. All array of both teaching and technical staff as well as students need to know to a reasonable extent about the issues and challenges in the use of ICT for education (Ogbomo. E.F, 2011). It has been severally been suggested in various academic climes of the need for teachers and students to be above reproach as succinctly put by Crossley. S.A. & McNamara, D.S, 2021 ‘in understanding the basic issues (effectiveness, cost, equity, and sustainability), as well as the challenges (infrastructure related challenges, capacity building challenges, challenges related to financing the cost of ICT use, to mention but few) surrounding the use of ICT in education and then apply those issues as principles in practice’. The essence of this study is to attempt presenting the appropriate methods in which ARM X86, CISC and RISC can be taught with ease for students in Nigerian Universities to the effect that Institutions lack adequate number of computers and relevant ICT accessories and/or soft and hardwires in laboratories. The methods which was used initially was making use of Projectors for the students in their class rooms and the use of microphone speakers to teach the students in addition to having to cope with extended lectures periods as a result of downtimes. The hindrances notwithstanding, when this method was initiated students had a better theoretical understanding of ARM X86, CISC and RISC because as in agreement with the submission of Bhandarkar. D&Clark. W.D, 1991; in order to achieve results better comprehension and quicker understanding by Students, videos were deployed as lectures were on-going to augment the prospects and constraints of the teaching and delivery of computer architecture. When various methods (Wireless LAN (WLAN), computers/laptops, and other technologies were taken into cognizance, in the teaching and practical delivery of computer architecture, it was observed that the students’ comprehension and understanding of the Reduced Instruction Sets of Computers and the Complex Instruction Sets of Computers showed remarkable improvement.

Adding 32-bit Mode to the ACL2 Model of the x86 ISA

The ACL2 model of the x86 Instruction Set Architecture was built for the 64-bit mode of operation of the processor. This paper reports on our work to extend the model with support for 32-bit mode, recounting the salient aspects of this activity and identifying the ones that required the most work.

The x86isa Books: Features, Usage, and Future Plans

The x86isa library, incorporated in the ACL2 community books project, provides a formal model of the x86 instruction-set architecture and supports reasoning about x86 machine-code programs. However, analyzing x86 programs can be daunting -- even for those familiar with program verification, in part due to the complexity of the x86 ISA. Furthermore, the x86isa library is a large framework, and using and/or contributing to it may not seem straightforward. We present some typical ways of working with the x86isa library, and describe some of its salient features that can make the analysis of x86 machine-code programs less arduous. We also discuss some capabilities that are currently missing from these books -- we hope that this will encourage the community to get involved in this project.

SHRINK: Reducing the ISA complexity via instruction recycling

Microprocessor manufacturers typically keep old instruction sets in modern processors to ensure backward compatibility with legacy software. The introduction of newer extensions to the ISA increases the design complexity of microprocessor front-ends, exacerbates the consumption of precious on-chip resources (e.g., silicon area and energy), and demands more efforts for hardware verification and debugging. We analyzed several x86 applications and operating systems deployed between 1995 and 2012 and observed that many instructions stop being used over time, and more than 500 instructions were never used in these applications. We also investigate the impact of including these unused instructions in the design of the x86 decoders and propose SHRINK, a mechanism to remove old instructions without breaking backward compatibility with legacy code. SHRINK allows us to remove 40% of the instructions from the x86 ISA and improve the critical path, area, and power consumption of the instruction decoder, respectively, by 23%, 48%, and 49%, on average.

ISA Wars

RISC versus CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing landscape is significantly different: Growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA). Furthermore, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. Thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important again, and we seek to answer this question through a detailed measurement-based study on real hardware running real applications. We analyze measurements on seven platforms spanning three ISAs (MIPS, ARM, and x86) over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors’ performance and energy efficiency. We find that ARM, MIPS, and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant.

Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA

The potential performance of superscalar processors can be exploited only when processor is fed with sufficient instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs could not support instruction streaming beyond a basic block. In x86 processors, the split-line instruction problem worsens this situation. In this paper, we proposed a basic blocks reassembling ISB. By cooperating with the proposed Line-Weighted Branch Target Buffer (LWBTB), the proposed ISB can predict upcoming branch information and reassemble current cache line together with the other cache line containing instructions for the next basic block. Therefore, the fetcher could fetch more instructions in a cycle with the assistance of the proposed ISB. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks present in a reassembled cache line and the fetch efficiency is about 90% as the fetch capacity is under 6.

MPTLsim

The introduction of multicore microprocessors in the recent years has made it imperative to use cycleaccurate and full-system simulators in the architecture research community. We introduce MPTLsim - a multicore simulator for the X86 ISA that meets this need. MPTLsim is a uop-accurate, cycle-accurate, full-system simulator for multicore designs based on the X86-64 ISA. MPTLsim extends PTLsim, a publicly available single core simulator, with a host of additional features to support hyperthreading within a core and multiple cores, with detailed models for caches, on-chip interconnections and the memory data flow. MPTLsim incorporates detailed simulation models for cache controllers, interconnections and has built-in implementations of a number of cache coherency protocols.

Reducing Startup Time in Co-Designed Virtual Machines

A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventional (legacy) ISA into optimized code for an underlying implementation-specific ISA. Because translation is done dynamically, an important consideration in such systems is the startup time for performing the initial translations. Beginning with a previously proposed co-designed VM that implements the x86 ISA, we study runtime binary translation overhead effects. The co-designed x86 virtual machine is based on an adaptive translation system that uses a basic block translator for initial emulation and a superblock translator for hotspot optimization. We analyze and model VM startup performance via simulation. We observe that non-hotspot emulation via basic block translation is the major part of the startup overhead. To reduce startup translation overhead, we follow the co-designed hardware / software philosophy and propose hardware assists to dramatically accelerate basic block translations. By combining hardware assists with balanced translation strategies, the co-designed translation system reduces runtime overhead significantly and demonstrates very competitive startup performance when compared with conventional processors running a set of Windows application benchmarks.