WSe2 Transistors Research Articles

Low Contact Resistance WSe2 p-Type Transistors with Highly Stable, CMOS-Compatible Dopants.

High contact resistance has been a bottleneck in developing high-performance transition-metal dichalcogenide (TMD) based p-type transistors. We report degenerately doped few-layer WSe2 transistors with contact resistance as low as 0.23 ± 0.07 kΩ·μm per contact by using platinum(IV) chloride (PtCl4) as the p-type dopant, which is composed of ions compatible with the complementary metal-oxide-semiconductor (CMOS) fabrication process. Top-gated devices with a gate length of 200 nm showed good switching behaviors, implying that the dopant diffusion into the gate stack is not significant. The devices showed nearly identical performance after being kept in air for 86 days without any encapsulation while retaining the degenerately doped states at 78 K with pressure lower than 10-5 Torr, highlighting the stability of the dopants. The presented method sets forth the availability of highly stable methods for pattern doping the transistors with a thinned Schottky barrier width for low contact resistance devices.

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

Dual-Mode Reconfigurable Split-Gate Logic Transistor through Van der Waals Integration.

As silicon-based transistors approach their physical size limitations, two-dimensional material-based reconfigurable functional electronic devices are considered the most promising novel device architectures beyond Moore strategies. While these devices have garnered significant attention, they often require complex device fabrication processes and extra electric fields. Additionally, the device performance is usually limited by the metal-semiconductor interface properties. In this Letter, we have constructed a reconfigurable logic device based on a WSe2 transistor with a nanofloating gate and split-gates through van der Waals integration. This device achieves a small Schottky barrier height due to the van der Waals contacts. By varying the split-gate biases, we can realize volatile reconfigurable homojunctions as well as AND, OR, NOR, and NAND logic operations with just a single device. Furthermore, with the charge trapping effect of nanofloating gate, we can also achieve nonvolatile reconfigurable homojunctions, as well as AND and OR logic operations. The volatile and nonvolatile logic operations are similar to the short-term plasticity and long-term plasticity, respectively, of synapses in the human brain. This work offers a potential approach for creating novel reconfigurable functional electronic devices with a simple fabrication process and low cost.

High-Performance p-Type Quasi-Ohmic of WSe2 Transistors Using Vanadium-Doped WSe2 as Intermediate Layer Contact.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs), such as tungsten diselenide (WSe2), hold immense potential for applications in electronic and optoelectronic devices. However, a significant Schottky barrier height (SBH) at the metal-semiconductor (MS) interface reduces the electronic device performance. Here, we present a unique 2D/2D contact method for minimizing contact resistance and reducing the SBH. This approach utilizes vanadium-doped WSe2 (V-WSe2) as the drain and source contacts. The fabricated transistor exhibited a stable operation with p-type quasi-ohmic contact and a high on/off current ratio surpassing 108 at room temperature, reaching 1011 at 10 K. The device achieved an on-current of 68.87 μA, a high mobility of 103.80 cm2 V-1 s-1, a low contact resistance of 0.92 kΩ, and remarkably low SBH values of 1.51 meV for holes at VGS = -120 V with fixed VDS = 1 V. Furthermore, a Schottky photodiode has been fabricated, utilizing V-WSe2 and Cr as the asymmetric contact platform, showing a responsivity of 116 mA W1-. The findings of this study suggest a simple and efficient method for improving the performance of TMDC-based transistors.

Biaxial Strain Transfer in Monolayer MoS2 and WSe2 Transistor Structures.

Monolayer transition metal dichalcogenides are intensely explored as active materials in 2D material-based devices due to their potential to overcome device size limitations, sub-nanometric thickness, and robust mechanical properties. Considering their large band gap sensitivity to mechanical strain, single-layered TMDs are well-suited for strain-engineered devices. While the impact of various types of mechanical strain on the properties of a variety of TMDs has been studied in the past, TMD-based devices have rarely been studied under mechanical deformations, with uniaxial strain being the most common one. Biaxial strain on the other hand, which is an important mode of deformation, remains scarcely studied as far as 2D material devices are concerned. Here, we study the strain transfer efficiency in MoS2- and WSe2-based flexible transistor structures under biaxial deformation. Utilizing Raman spectroscopy, we identify that strains as high as 0.55% can be efficiently and homogeneously transferred from the substrate to the material in the transistor channel. In particular, for the WSe2 transistors, we capture the strain dependence of the higher-order Raman modes and show that they are up to five times more sensitive compared to the first-order ones. Our work demonstrates Raman spectroscopy as a nondestructive probe for strain detection in 2D material-based flexible electronics and deepens our understanding of the strain transfer effects on 2D TMD devices.

Controlled Fabrication of Metallic MoO2 Nanosheets towards High-Performance p-Type 2D Transistors.

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) are extensively employed as channel materials in advanced electronic devices. The electrical contacts between electrodes and 2D semiconductors play a crucial role in the development of high-performance transistors. While numerous strategies for electrode interface engineering have been proposed to enhance the performance of n-type 2D transistors, upgrading p-type ones in a similar manner remains a challenge. In this work, significant improvements in a p-type WSe2 transistor are demonstrated by utilizing metallic MoO2 nanosheets as the electrode contact, which are controllably fabricated through physical vapor deposition and subsequent annealing. The MoO2 nanosheets exhibit an exceptional electrical conductivity of 8.4 × 104 S m‒1 and a breakdown current density of 3.3 × 106 A cm‒2. The work function of MoO2 nanosheets is determined to be ≈5.1eV, making them suitable for contacting p-type 2D semiconductors. Employing MoO2 nanosheets as the electrode contact in WSe2 transistors results in a notable increase in the field-effect mobility to 92.0 cm2 V‒1 s‒1, which is one order of magnitude higher than the counterpart devices with conventional electrodes. This study not only introduces an intriguing 2D metal oxide to improve the electrical contact in p-type 2D transistors, but also offers an effective approach to fabricating all-2D devices.

Low Resistance Contact to P-Type Monolayer WSe2.

Advanced microelectronics in the future may require semiconducting channel materials beyond silicon. Two-dimensional (2D) semiconductors, with their atomically thin thickness, hold great promise for future electronic devices. One challenge to achieving high-performance 2D semiconductor field effect transistors (FET) is the high contact resistance at the metal-semiconductor interface. In this study, we develop a charge-transfer doping strategy with WSe2/α-RuCl3 heterostructures to achieve low-resistance ohmic contact for p-type monolayer WSe2 transistors. We show that hole doping as high as 3 × 1013 cm-2 can be achieved in the WSe2/α-RuCl3 heterostructure due to its type-III band alignment, resulting in an ohmic contact with resistance of 4 kΩ μm. Based on that, we demonstrate p-type WSe2 transistors with an on-current of 35 μA·μm-1 and an ION/IOFF ratio exceeding 109 at room temperature.

Two‐Dimensional Heterostructure Complementary Logic Enabled by Optical Writing

Integrated logic circuits using atomically thin, two‐dimensional (2D) materials offer several potential advantages compared to established silicon technologies such as increased transistor density, circuit complexity, and lower energy dissipation leading to scaling benefits. In this article, a novel approach to achieve tunable doping in 2D semiconductors is explored to achieve complementary transistors and logic integration. By selectively transferring WSe2 onto hBN and SiO2 substrates, complementary transistor behavior (n‐ and p‐type) was achieved using a UV light source and electrostatic activation. Furthermore, advanced characterization techniques, including high‐resolution transmission electron microscopy (HRTEM) and Kelvin probe force microscopy (KPFM), provided insights into the chemical composition and surface potential changes after UV writing. Finally, a logic inverter was successfully implemented using selectively photo‐induced doped WSe2 transistors, showcasing the potential for practical logic applications. This innovative method opens new avenues for designing energy‐efficient and reconfigurable 2D semiconductor circuits, addressing key challenges in modern electronics.

Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide.

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al2O3) onto tungsten diselenide (WSe2). By utilizing the Al2O3 passivation layer, we observed precisely tuned n-type behavior in contrast to transistors fabricated on the as-grown WSe2 film without any passivation layer, which display prominent p-type behavior. The polarity-transformed n-type WSe2 transistor from the pristine p-type shows the maximum ON current of ∼0.1 μA accompanied by a high electron mobility of 7 cm2 V-1 s-1 at a drain voltage (VDS) of 1 V. We successfully showcased a homogeneous CMOS inverter utilizing 2D-TMDC which exhibits an impressive voltage gain of 7 at VDD = 5 V. Moreover, this effective polarity control approach was further expanded upon to successfully demonstrate a range of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. The proposed methodology possesses significant promise for facilitating the advancement of high-density circuitry components utilizing 2D-TMDC.

PVA-assisted metal transfer for vertical WSe2 photodiode with asymmetric van der Waals contacts

Abstract The vertical electronic and optoelectronic devices based on 2D materials have shown great advantages over lateral devices, such as higher current density, faster switch speed, and superior short-channel control. However, it is difficult to fabricate vertical device with conventional metal deposition methods due to the aggressive process usually results in damage to the contact region. Here, we develop a simple and effective metal transfer technique and fabricate p-type and n-type WSe2 transistors by using metals with different work functions and subsequently create a vertical WSe2 transistors with a 18-nm-thick channel, which retain good gate coupling effect. Furthermore, a vertical WSe2 photodiode is constructed with graphene and Pt as asymmetric van der Waals (vdW) contacts. The work-function difference between graphene and Pt generates a built-in electric filed, leading to a high current rectification over 105. Under 405 nm laser illumination, the device exhibits excellent self-powered photodetection properties, including a high responsivity of 0.28 A W−1, fast response speed of 24 μs, and large light on/off ratio exceeding 105 at zero bias, which surpass most of the vdW photodiodes. This work demonstrates that the metal transfer technique is a promising strategy for the construction of high-performance vertical optoelectronic devices.

Alleviation of Schottky barrier heights at TMDs/metal interfaces with a tunneling layer of semiconducting InSe nanoflake

Two-dimensional transition metal dichalcogenides (TMDs) are promising for post-Moore electronic applications, however, the device performance is strongly limited by the large Schottky barrier height (SBH) at TMDs/metal interfaces. Herein, by carrying out conductive atomic force microscopy (C-AFM), temperature-dependent transport measurements, and density functional theory (DFT) calculations, it is demonstrated that the insertion of a two-dimensional semiconductor InSe between metal and TMDs can effectively alleviate the SBHs with preservation of high tunneling efficiency, and enhance the device performance of both p-type WSe2 and n-type MoS2 transistors. Specifically, SBHs in MoS2 and WSe2 transistors were reduced from 156 to 33 meV and from 95 to 16 meV, respectively, giving rise to dramatically improved on-state current and carrier mobilities of the devices. This is attributed to the coupling effects from Fermi level pinning between metal and InSe, optimized hybrid electronic structure and appropriate band alignment of InSe/TMD heterostructures. Our work provides an avenue to tailor the contact engineering of TMDs devices by inserting appropriate 2D materials guided from the band alignment of the heterostructures.

Bioinspired Artificial Visual System Based on 2D WSe2 Synapse Array

AbstractMachine vision systems that capture images for visual inspection and recognition tasks must be able to perceive, memorize, and compute any color scene. To achieve this, most of the current visual systems use circuits and algorithms which may reduce efficiency and increase complexity. Herein, a 2D semiconductor tungsten diselenide (WSe2)‐based phototransistor that successfully demonstrates an artificial vision system integrating the processing capability of visual information sensing memory, is reported. Furthermore, based on a 6 × 6 fabricated retinal perception array, artificial visual information sensing memory and processing system are proposed to perform image recognition tasks, which can avoid the time delay and energy consumption caused by data conversion and movement. On the other hand, highly linear symmetric synaptic plasticity can be achieved based on the modulation of carrier types in WSe2 transistors with different thicknesses, facilitating the high level of training and inference accuracy for artificial neural networks. Last, through training and inference simulations, the feasibility of the hybrid synapses for optical neural networks (ONN) is demonstrated.

Charge transfer enabled by the p-doping of WSe2 for 2D material-based printable electronics

Here, we report the fabrication of high-performance printable WSe2 transistors via the doping of p-type FeCl3 molecules (hole mobility: ∼1.5 cm2 V−1 s−1; on/off ratio: ∼106). A complementary inverter is demonstrated with p-WSe2 and n-MoS2 transistors, which highlights its potential for application in future two-dimensional material-based printable electronics.

High-Performance Artificial Synapse Based on CVD-Grown WSe2 Flakes with Intrinsic Defects

High-performance artificial synaptic devices with rich functions are highly desired for the development of an advanced brain-like neuromorphic system. Here, we prepare synaptic devices based on a CVD-grown WSe2 flake, which has an unusual morphology of nested triangles. The WSe2 transistor exhibits robust synaptic behaviors such as excitatory postsynaptic current, paired-pulse facilitation, short-time plasticity, and long-time plasticity. Furthermore, due to its high sensitivity to light illumination, the WSe2 transistor exhibits excellent light-dosage-dependent and light wavelength-dependent plasticity, which endow the synaptic device with more intelligent learning and memory functions. In addition, WSe2 optoelectronic synapses can mimic "learning experience" behavior and associative learning behavior like the brain. An artificial neural network is simulated for pattern recognition of hand-written digital images in the MNIST data set and the best recognition accuracy could reach 92.9% based on weight updating training of our WSe2 device. Detailed surface potential analysis and PL characterization reveal that the intrinsic defects generated in growth are dominantly responsible for the controllable synaptic plasticity. Our work suggests that the CVD-grown WSe2 flake with intrinsic defects capable of robust trapping/de-trapping charges holds great application prospects in future high-performance neuromorphic computation.

Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2 SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

High-Mobility Flexible Transistors with Low-Temperature Solution-Processed Tungsten Dichalcogenides

The investigation of high-mobility two-dimensional (2D) flakes beyond molybdenum disulfide (MoS2) will be necessary to create a library of high-mobility solution-processed networks that conform to substrates and remain functional over thousands of bending cycles. Here we report electrochemical exfoliation of large-aspect-ratio (>100) semiconducting flakes of tungsten diselenide (WSe2) and tungsten disulfide (WS2) as well as MoS2 as a comparison. We use Langmuir-Schaefer coating to achieve highly aligned and conformal flake networks, with minimal mesoporosity (∼2-5%), at low processing temperatures (120 °C) and without acid treatments. This allows us to fabricate electrochemical transistors in ambient air, achieving average mobilities of μMoS2 ≈ 11 cm2 V-1 s-1, μWS2 ≈ 9 cm2 V-1 s-1, and μWSe2 ≈ 2 cm2 V-1 s-1 with a current on/off ratios of Ion/Ioff ≈ 2.6 × 103, 3.4 × 103, and 4.2 × 104 for MoS2, WS2, and WSe2, respectively. Moreover, our transistors display threshold voltages near ∼0.4 V with subthreshold slopes as low as 182 mV/dec, which are essential factors in maintaining power efficiency and represent a 1 order of magnitude improvement in the state of the art. Furthermore, the performance of our WSe2 transistors is maintained on polyethylene terephthalate (PET) even after 1000 bending cycles at 1% strain.

High-Performance Solution-Processed 2D P-Type WSe2 Transistors and Circuits through Molecular Doping.

Semiconducting ink based on 2D single-crystal flakes with dangling-bond-free surfaces enables the implementation of high-performance devices on form-free substrates by cost-effective and scalable printing processes. However, the lack of solution-processed p-type 2D semiconducting inks with high mobility is an obstacle to the development of complementary integrated circuits. Here, a versatile strategy of doping with Br2 is reported to enhance the hole mobility by orders of magnitude for p-type transistors with 2D layered materials. Br2 -doped WSe2 transistors show a field-effect hole mobility of more than 27cm2 V-1 s-1 , and a high on/off current ratio of ≈107 , and exhibits excellent operational stability during the on-off switching, cycling, and bias stressing testing. Moreover, complementary inverters composed of patterned p-type WSe2 and n-type MoS2 layered films are demonstrated with an ultra-high gain of 1280 under a driving voltage (VDD ) of 7V. This work unveils the high potential of solution-processed 2D semiconductors with low-temperature processability for flexible devices and monolithic circuitry.

Low‐Power Logic‐in‐Memory Complementary Inverter Based on p‐WSe2 and n‐WS2

AbstractTransition metal dichalcogenides have been considered as candidate materials to construct logic‐in‐memory devices for realizing non‐von‐Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low‐power logic‐in‐memory device is demonstrated by constructing complementary inverter with p‐WSe2 and n‐WS2 transistors. By engineering the interface states between WSe2 (WS2) and substrate artificially, non‐volatile memory with resistance ratio of 104 and 103 after 500 s are achieved in individual WSe2 and WS2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p‐WSe2 and n‐WS2 transistors. More importantly, the static operating source‐drain current Ids of this inverter is around 0.5/0.1 nA at low/high resistance states with source‐drain voltage Vds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non‐von‐Neumann device toward post‐Moore information processing technology.

High-Temperature Annealing Effects on Atomically Thin Tungsten Diselenide Field-Effect Transistor

Two-dimensional (2D) material-based devices are expected to operate under high temperatures induced by Joule heating and environmental conditions when integrated into compact integrated circuits for practical applications. However, the behavior of these materials at high operating temperatures is obscure as most studies emphasize only room temperature or low-temperature operation. Here, the high-temperature electrical response of the tungsten diselenide (WSe2) field-effect transistor was studied. It is revealed that 350 K is the optimal annealing temperature for the WSe2 transistor, and annealing at this temperature improves on-current, field-effect mobility and on/off ratio around three times. Annealing beyond this temperature (360 K to 670 K) adversely affects the device performance attributed to the partial oxidation of WSe2 at higher temperatures. An increase in hysteresis also confirms the formation of new traps as the device is annealed beyond 350 K. These findings explicate the thermal stability of WSe2 and can help design 2D materials-based durable devices for high-temperature practical applications.

Synthesis of 2D α‐GeTe Single Crystals and α‐GeTe/WSe2 Heterostructures with Enhanced Electronic Performance

AbstractTwo‐dimensional (2D) materials have attracted extensive attention due to their important prospects in electronics and optoelectronics. Synthesizing new 2D materials, characterizing their properties, and developing their applications are still important topics. Herein, the synthesis of α‐GeTe nanoplates on different substrates via the chemical vapor deposition process and the systematical investigation of their structure and electrical properties, is reported. By controlling the synthesis temperature and carrier gas, α‐GeTe nanoplates, with a lateral dimension up to 30 µm and a thickness down to 1.2 nm, which corresponds to the thickness of one unit cell, can be obtained on 2D WSe2 substrate. Electrical transport studies show 2D α‐GeTe nanoplates have an excellent conductivity (9.33 × 105 S m−1) and an extraordinary breakdown current density (6.1× 107 A cm−2). Compared with traditional WSe2 transistors with deposited metal electrodes, the WSe2 transistors with the metallic α‐GeTe nanoplates as van der Waals metal electrodes achieved much better performance, such as higher on‐state current (from 7.83 to 23.23 µA µm−1) and electron mobility (from 16.5 to 75.0 cm2 V1 S1). This study demonstrates an effective pathway to achieve ultrathin 2D materials and provides an accessible strategy to improve the performance of 2D electronic devices.