WSe2 Field-effect Transistors Research Articles

Reduced interface effect of proton beam irradiation on the electrical properties of WSe2/hBN field effect transistors

Two-dimensional transition metal dichalcogenide (TMDC) semiconductors are emerging as strong contenders for electronic devices that can be used in highly radioactive environments such as outer space where conventional silicon-based devices exhibit nonideal characteristics for such applications. To address the radiation-induced interface effects of TMDC-based electronic devices, we studied high-energy proton beam irradiation effects on the electrical properties of field-effect transistors (FETs) made with tungsten diselenide (WSe2) channels and hexagonal boron-nitride (hBN)/SiO2 gate dielectrics. The electrical characteristics of WSe2 FETs were measured before and after the irradiation at various proton beam doses of 1013, 1014, and 1015 cm−2. In particular, we demonstrated the dependence of proton irradiation-induced effects on hBN layer thickness in WSe2 FETs. We observed that the hBN layer reduces the WSe2/dielectric interface effect which would shift the transfer curve of the FET toward the positive direction of the gate voltage. Also, this interface effect was significantly suppressed when a thicker hBN layer was used. This phenomenon can be explained by the fact that the physical separation of the WSe2 channel and SiO2 dielectric by the hBN interlayer prevents the interface effects originating from the irradiation-induced positive trapped charges in SiO2 reaching the interface. This work will help improve our understanding of the interface effect of high-energy irradiation on TMDC-based nanoelectronic devices.

High-Performance Contact-Doped WSe2 Transistors Using TaSe2 Electrodes.

Two-dimensional (2D) transitional metal dichalcogenides (TMDs) have garnered significant attention due to their potential for next-generation electronics, which require device scaling. However, the performance of TMD-based field-effect transistors (FETs) is greatly limited by the contact resistance. This study develops an effective strategy to optimize the contact resistance of WSe2 FETs by combining contact doping and 2D metallic electrode materials. The contact regions were doped using a laser, and the metallic TaSe2 flakes were stacked on doped WSe2 as electrodes. Doping the contact areas decreases the depletion width, while introducing the TaSe2 contact results in a lower Schottky barrier. This method significantly improves the electrical performance of the WSe2 FETs. The doped WSe2/TaSe2 contact exhibits an ultralow Schottky barrier height of 65 meV and a contact resistance of 11 kΩ·μm, which is a 50-fold reduction compared to the conventional Cr/Au contact. Our method offers a way on fabricating high-performance 2D FETs.

Multi-Layer Palladium Diselenide as a Contact Material for Two-Dimensional Tungsten Diselenide Field-Effect Transistors.

Tungsten diselenide (WSe2) has emerged as a promising ambipolar semiconductor material for field-effect transistors (FETs) due to its unique electronic properties, including a sizeable band gap, high carrier mobility, and remarkable on-off ratio. However, engineering the contacts to WSe2 remains an issue, and high contact barriers prevent the utilization of the full performance in electronic applications. Furthermore, it could be possible to tune the contacts to WSe2 for effective electron or hole injection and consequently pin the threshold voltage to either conduction or valence band. This would be the way to achieve complementary metal-oxide-semiconductor devices without doping of the channel material.This study investigates the behaviour of two-dimensional WSe2 field-effect transistors with multi-layer palladium diselenide (PdSe2) as a contact material. We demonstrate that PdSe2 contacts favour hole injection while preserving the ambipolar nature of the channel material. This consequently yields high-performance p-type WSe2 devices with PdSe2 van der Waals contacts. Further, we explore the tunability of the contact interface by selective laser alteration of the WSe2 under the contacts, enabling pinning of the threshold voltage to the valence band of WSe2, yielding pure p-type operation of the devices.

Potassium hydroxide treatment of layered WSe2 with enhanced electronic performances.

2D WSe2-based electronic devices have received much research interest. However, it is still a challenge to achieve high electronic performance in WSe2-based devices. In this work, we report greatly enhanced performances of different thickness WSe2 ambipolar transistors and demonstrate homogeneous WSe2 inverter devices, which are obtained by using a semiconductor processing-compatible layer removal technique via chemical removal of the surface top WOx layer formed by O2 plasma treatment. Importantly, monolayer WSe2 was realised after several consecutive removal processes, demonstrating that the single layer removal is accurate and reliable. After subsequent removal of the top layer WOx by KOH, the fabricated WSe2 field-effect transistors exhibit greatly enhanced electronic performance along with the high electron and hole mobilities of 40 and 85 cm2 V-1 s-1, respectively. Our work demonstrates that the layer removal technique is an efficient route to fabricate high performance 2D material-based electronic devices.

Controlled synthesis of van der Waals CoS2 for improved p-type transistor contact

Two-dimensional (2D) van der Waals (vdW) p-type semiconductors have shown attractive application prospects as atomically thin channels in electronic devices. However, the high Schottky hole barrier of p-type semiconductor–metal contacts induced by Fermi-level pinning is hardly removed. Herein, we prepare a vdW 1T-CoS2 nanosheet as the contact electrode of a WSe2 field-effect transistor (FET), which shows a considerably high on/off ratio > 107 and a hole mobility of ∼114.5 cm2 V−1 s−1. The CoS2 nanosheets exhibit metallic conductivity with thickness dependence, which surpasses most 2D transition metal dichalcogenide metals or semimetals. The excellent FET performance of the CoS2-contacted WSe2 FET device can be attributed to the high work function of CoS2, which lowers the Schottky hole barrier. Our work provides an effective method for growing vdW CoS2 and opens up more possibilities for the application of 2D p-type semiconductors in electronic devices.

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping.

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors.

Atomically thin monolayer two-dimensional (2D) semiconductors with natural immunity to short channel effects are promising candidates for sub-10 nm very large-scale integration technologies. Herein, the ultimate limit in optoelectronic performances of monolayer WSe2 field-effect transistors (FETs) is examined by constructing a sloping channel down to 6 nm. Using a simple scaling method compatible with current micro/nanofabrication technologies, we achieve a record high saturation current up to 1.3 mA/μm at room temperature, surpassing any reported monolayer 2D semiconductor transistors. Meanwhile, quasi-ballistic transport in WSe2 FETs is first demonstrated; the extracted high saturation velocity of 4.2 × 106 cm/s makes it suitable for extremely sensitive photodetectors. Furthermore, the photoresponse speed can be improved by reducing channel length due to an electric field-assisted detrapping process of photogenerated carriers in localized states. As a result, the sloping-channel device exhibits a faster response, higher detectivity, and additional polarization resolution ability compared to planar micrometer-scale devices.

P-Type Conversion of WS2 and WSe2 by Position-Selective Oxidation Doping and Its Application in Top Gate Transistors.

For the complementary operation of two-dimensional (2D) material-based field-effect transistors (FETs), high-performance p-type FETs are essential. In this study, we applied surface charge-transfer doping from WOx, which has a large work function of ∼6.5 eV, selectively to the access region of WS2 and WSe2 by covering the channel region with h-BN. By reducing the Schottky barrier width at the contact and injecting holes into the valence band, the p-type conversion of intrinsically n-type trilayer WSe2 FET was successfully achieved. However, trilayer WS2 did not show clear p-type conversion because its valence band maximum is 0.66 eV lower than that of trilayer WSe2. Although inorganic WOx boasts high air stability and fabrication process compatibility due to its high thermal budget, the trap sites in WOx cause large hysteresis during back gate operation of WSe2 FETs. However, by using top gate (TG) operation with an h-BN protection layer as a TG insulator, a high-performance p-type WSe2 FET with negligible hysteresis was achieved.

Se-Vacancy Healing with Substitutional Oxygen in WSe2 for High-Mobility p-Type Field-Effect Transistors.

Transition-metal dichalcogenides possess high carrier mobility and can be scaled to sub-nanometer dimensions, making them viable alternative to Si electronics. WSe2 is capable of hole and electron carrier transport, making it a key component in CMOS logic circuits. However, since the p-type electrical performance of the WSe2-field effect transistor (FET) is still limited, various approaches are being investigated to circumvent this issue. Here, we formed a heterostructural multilayer WSe2 channel and solution-processed aluminum-doped zinc oxide (AZO) for compositional modification of WSe2 to obtain a device with excellent electrical properties. Supplying oxygen anions from AZO to the WSe2 channel eliminated subgap states through Se-deficiency healing, resulting in improved transport capacity. Se vacancies are known to cause mobility degradation due to scattering, which is mitigated through ionic compensation. Consequently, the hole mobility can reach high values, with a maximum of approximately 100 cm2/V s. Further, the transport behavior of the oxygen-doped WSe2-FET is systematically analyzed using density functional theory simulations and photoexcited charge collection spectroscopy measurements.

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation.

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2 ) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2 , combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. Theunique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.

Anisotropy of impact ionization in WSe2 field effect transistors

Carrier multiplication via impact ionization in two-dimensional (2D) layered materials is a very promising process for manufacturing high-performance devices because the multiplication has been reported to overcome thermodynamic conversion limits. Given that 2D layered materials exhibit highly anisotropic transport properties, understanding the directionally-dependent multiplication process is necessary for device applications. In this study, the anisotropy of carrier multiplication in the 2D layered material, WSe2, is investigated. To study the multiplication anisotropy of WSe2, both lateral and vertical WSe2 field effect transistors (FETs) are fabricated and their electrical and transport properties are investigated. We find that the multiplication anisotropy is much bigger than the transport anisotropy, i.e., the critical electric field (ECR) for impact ionization of vertical WSe2 FETs is approximately ten times higher than that of lateral FETs. To understand the experimental results we calculate the average energy of the carriers in the proposed devices under strong electric fields by using the Monte Carlo simulation method. The calculated average energy is strongly dependent on the transport directions and we find that the critical electric field for impact ionization in vertical devices is approximately one order of magnitude larger than that of the lateral devices, consistent with experimental results. Our findings provide new strategies for the future development of low-power electric and photoelectric devices.Graphical

Effects of Oxygen Plasma Treatment on Fermi‐Level Pinning and Tunneling at the Metal–Semiconductor Interface of WSe2 FETs

AbstractRecently, 2D materials have been intensively investigated for their novel nanoelectronic applications; among these materials, tungsten diselenide (WSe2) is attracting substantial research interest due to its high mobility, sizable bandgap, and ambipolar characteristics. However, Fermi‐level pinning (FLP) at the metal–semiconductor contact is a critical issue preventing further integration of WSe2 to complementary metal–oxide–semiconductor (CMOS) technology. In this study, a facile doping method of oxygen (O2) plasma treatment and an aging effect to overcome the FLP of WSe2 field‐effect transistors (FETs) are utilized. After aging, a reduction is observed in FLP on oxidized WSe2 FETs, along with a decrease in pinning factor (S) for holes from −0.06 to −0.36. Further, the field‐effect mobility of high‐ (Pd) and low‐ (In) work‐function contacted WSe2 devices indicates the presence of more improvement in high‐work‐function metal‐contacted p‐type WSe2 FETs, which further strengthens the Fermi level de‐pinning behavior attributed to the O2 plasma and aging processes. The existence of different tunneling behaviors of Pd and In devices also confirms the effect of O2 plasma doping into WSe2 FETs. Ultimately, this work demonstrates a simple and efficient method for achieving the de‐pinning of Fermi‐levels and modulating FLP of 2D FETs.

Comprehensive Polarity Regulation of WSe2 Field‐Effect Transistors Enabled by Combining Contact Engineering and Plasma Doping

Two‐dimensional semiconductors are considered as promising candidates in next‐generation nanoelectronics. The polarity regulation, however, has been a great obstacle to their applications. Herein, a strategy to comprehensively modulate the polarity of WSe2 field‐effect transistors (FETs) by combining contact engineering and plasma doping is demonstrated. N‐type and ambipolar WSe2 FETs are obtained by indium (In) and chromium (Cr) contact, respectively. Meanwhile Cr contact and mild oxygen plasma doping are employed simultaneously to realize p‐type WSe2 FET. High on/off ratio of ≈107 has been achieved for both n‐type and p‐type WSe2 FETs. Subsequently, they are connected in series to construct a homogeneous complementary logic inverter and a lateral p–n diode. Anti‐ambipolar transfer characteristics, therefore, are accessed from the inverter. And the forward to backward rectifying ratio reaches 106 for the p–n diode. The proposed strategy paves the way for practical applications of WSe2 FETs in logic circuits and optoelectronics.

(Invited, Digital Presentation) Low Voltage Operation of CMOS Inverter Based on WSe2 n/p FETs

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs.For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively.Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts.Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V.Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits.

Anodic tantalum: Fabrication, breakdown characteristics of capacitor and integration with a WSe2 field effect transistor

The anodization of metals is a simple and low cost method of producing metal-oxides. This article discusses the procedure for anodizing tantalum (Ta) and details the characterization of capacitors formed by tantalum pentoxide (Ta2O5) dielectric. The breakdown field for the un-annealed, 200 °C and 400 °C annealed samples are 5.4, 5.1 and 3.3 MV/cm respectively. A number of factors affect the electrical properties of dielectrics and from our experiments, we observe that at an annealing temperature of 200 °C and pressure of 7.5 Torr, the dominant conduction mechanism of the capacitor changed from Schottky Emission to Poole-Frenkel Emission. In addition, we report the deposition of exfoliated WSe2 on anodic tantalum using the scotch tape method. Good adhesion has been observed between the WSe2 flakes and the anodic tantalum with obvious colour variation in relation to the thickness of the WSe2. Subsequently, a WSe2 Field Effect Transistor (FET) has been designed and fabricated using a mask-less lithographic technique. The anodic tantalum has been used as the gate dielectric while the bulk Ta as the back gate electrode. The transfer characteristics of the integrated device have been discussed, showing promise for low power operation.

Selective Electron Beam Patterning of Oxygen-Doped WSe2 for Seamless Lateral Junction Transistors.

Surface charge transfer doping (SCTD) using oxygen plasma to form a p‐type dopant oxide layer on transition metal dichalcogenide (TMDs) is a promising doping technique for 2D TMDs field‐effect transistors (FETs). However, patternability of SCTD is a key challenge to effectively switch FETs. Herein, a simple method to selectively pattern degenerately p‐type (p+)‐doped WSe2 FETs via electron beam (e‐beam) irradiation is reported. The effect of the selective e‐beam irradiation is confirmed by the gate‐tunable optical responses of seamless lateral p+–p diodes. The OFF state of the devices by inducing trapped charges via selective e‐beam irradiation onto a desired channel area in p+‐doped WSe2, which is in sharp contrast to globally p+‐doped WSe2 FETs, is realized. Selective e‐beam irradiation of the PMMA‐passivated p+‐WSe2 enables accurate control of the threshold voltage (V th) of WSe2 devices by varying the pattern size and e‐beam dose, while preserving the low contact resistance. By utilizing hBN as the gate dielectric, high‐performance WSe2 p‐FETs with a saturation current of −280 µA µm−1 and on/off ratio of 109 are achieved. This study's technique demonstrates a facile approach to obtain high‐performance TMD p‐FETs by e‐beam irradiation, enabling efficient switching and patternability toward various junction devices.

Heterogeneous Integration of Atomically Thin Semiconductors for Non-von Neumann CMOS.

Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high-performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n-type TMDs such as MoS2 and WS2 grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p-type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n-type MoS2 and p-type vanadium doped WSe2 FETs with non-volatile and analog memory storage capabilities to achieve a non-von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n-type and p-type FETs, which is critical for any IC development. Inverters and a simplified 2-input-1-output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non-von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.

Low-Temperature Synthesis of Boron Nitride as a Large-Scale Passivation and Protection Layer for Two-Dimensional Materials and High-Performance Devices.

Two-dimensional materials (2DMs) with extraordinary electronic and optical properties have attracted great interest in optoelectronic applications. Due to their atomically thin feature, 2DM-based devices are generally sensitive to oxygen and moisture in ambient air, and thus, practical application of durable 2DM-based devices remains challenging. Here, we report a novel strategy to directly synthesize amorphous BN film on various 2DMs and field-effect transistor (FET) devices at low temperatures by conventional chemical vapor deposition. The wafer-scale BN film with controllable thickness serves as a passivation and heat dissipation layer, further improving the long-term stability, the resistance to laser irradiation, and the antioxidation performance of the underneath 2DMs. In particular, the BN capping layer could be deposited directly on a WSe2 FET at low temperature to achieve a clean and conformal interface. The high performance of the BN-capped WSe2 device is realized with suppressed current fluctuations and 10-fold enhanced carrier mobility. The transfer-free amorphous BN synthesis technique is simple and applicable to various 2DMs grown on arbitrary substrates, which shows great potential for applications in future two-dimensional electronics.

Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching.

Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III-V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe2) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe2 channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe2 FET are systematically monitored during this layer-by-layer recess-channel process. The WSe2 etching rate is estimated to be 2-3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WOX) layer grown through ultraviolet-ozone treatment induces robust p-doping in the neighboring (or underlying) WSe2 through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe2 FETs enables the realization of a high on/off output current ratio (>108) and field-effect mobility (∼190 cm2/V·s), while maintaining low contact resistance (0.9-6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.