Write-back Policy Research Articles

CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile Memories

Emerging nonvolatile memories (NVMs), while exhibiting great potential to be DRAM alternatives, are vulnerable to security attacks. Secure NVM designs demand data persistence on top of traditional confidentiality and integrity protection. A simple adaption of existing secure memory designs would incur non-negligible overheads, including performance degradation, NVM lifetime reduction, and energy consumption increase. In this article, we propose CacheTree to address the integrity verification overhead for secure NVMs. By constructing extra Merkle trees (MTs) on top of metadata cache, CacheTree helps to authenticate the volatile cache contents, which enables the adoption of write-back policy and prevents frequent NVM writes in persisting metadata. We then adopt CacheTree to address the integrity verification in secure NVM, in particular, the overheads in persisting message authentication codes (for protecting the integrity of user data at memory line level) and persisting the main MT (for protecting the integrity of the whole memory space). Our experimental results show that CacheTree, with less than 0.5% storage overhead, achieves up to 20.1% performance improvement, 44.3% lifetime increase, and 43.7% energy consumption reduction over the state-of-the-art solutions.

A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement

High-capacity L4 architectures as a last-level cache (LLC) have been recently introduced between L3-SRAM and off-chip memory. These LLC architectures have either employed DRAM or spin-transfer torque (STT-RAM) memory technologies. It is a known fact that DRAM LLCs feature a higher energy consumption, while STT-RAM LLCs feature a lower write endurance compared to their counterparts. This paper proposes an efficient hybrid DRAM/STT-RAM LLC architecture that exploits the best characteristics offered by individual memory technologies while mitigating their drawbacks. More precisely, we introduce a novel mechanism for the storage and management of the hybrid LLC tags and a proactive L3-SRAM writeback policy that combines multiple dirty blocks that are mapped to the same LLC row. Our hybrid architecture reduces the LLC interference by having less writeback accesses and row fetches. The endurance is improved by reducing the number of STT-RAM block writes. We show that our LLC architecture reduces the total number of STT-RAM block writes by 78% and improves the average performance by 13% compared to a recently proposed STT-RAM LLC. Compared to the state-of-the-art DRAM LLC, we report an average energy and performance improvement of 24% and 17.1%, respectively.

Design, implementation, and evaluation of write-back policy with cache augmented data stores

The Cache Augmented Data Store (CADS) architecture extends a persistent data store with an in-memory cache manager. It is widely deployed to support read-intensive workloads. However, its write-around and write-through policies prevent the caching tier from absorbing write load. This means the data store layer must scale to process writes even when the extra capacity is not needed for read load. We address this limitation by devising a write-back technique to enable the caching layer to process both reads and writes. This technique preserves ACID transactions. We present a client side implementation of write-back and evaluate it using the YCSB, BG, and TPC-C benchmarks. In addition, we compare our write-back with (a) write-back policy of a data store such as MongoDB and (b) write-back policy of a host-side cache such as Flashcache.

Formal Modeling and Verification of a Victim DRAM Cache

The emerging Die-stacking technology enables DRAM to be used as a cache to break the “Memory Wall” problem. Recent studies have proposed to use DRAM as a victim cache in both CPU and GPU memory hierarchies to improve performance. DRAM caches are large in size and, hence, when realized as a victim cache, non-inclusive design is preferred. This non-inclusive design adds significant differences to the conventional DRAM cache design in terms of its probe, fill, and writeback policies. Design and verification of a victim DRAM cache can be much more complex than that of a conventional DRAM cache. Hence, without rigorous modeling and formal verification, ensuring the correctness of such a system can be difficult. The major focus of this work is to show how formal modeling is applied to design and verify a victim DRAM cache. In this approach, we identify the agents in the victim DRAM cache design and model them in terms of interacting state machines. We derive a set of properties from the specifications of a victim cache and encode them using Linear Temporal Logic. The properties are then proven using symbolic and bounded model checking. Finally, we discuss how these properties are related to the dataflow paths in a victim DRAM cache.

CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache

Stacked DRAM used as the last-level caches (LLCs) in multicore systems delivers performance enhancement due to its capacity benefit. While the performance of LLC depends heavily upon its block replacement policy, the conventional replacement policy needs redesigning to exploit the best of DRAM cache and avoid its drawbacks. The existing DRAM cache insertion policy blindly forwards victim lines replaced from L3 to the off-chip memory, regardless of the potential for increased hits by placing a fraction of them in the DRAM cache. Nevertheless, a naive design that steers all dirty victims to the DRAM cache introduces excessive writeback traffic, which aggravates capacity misses and DRAM interference. To leverage insertions in terms of writeback or fill requests, we propose a collective writeback and fill policy that adapts to the distinct access patterns of heterogeneous workloads based on runtime misses and writeback efficiency. The synthesis result shows that the new policy has only a small hardware overhead. According to the experimental results on the gem5 simulator, the new policy increases harmonic instruction per cycle throughput by 18%, 11.6%, and 11.7%, respectively, compared with the Always Writeback (AW)–Always Fill policy, Never Writeback Adaptive DRAM Placement policy, and AW Adaptive DRAM Placement policy on 64-MB alloy cache, while the improvement is 19.3%, 13.7%, and 14.5% on 64-MB MissMap cache.

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems

In resource-constrained embedded systems, on-chip cache memories play an important role in both performance and energy consumption. In contrast to read operations, scant regard has been paid to optimizing write operations even though the energy consumed by write operations in the data cache constitutes a large portion of the total energy consumption. Consequently, this paper proposes a write buffer-oriented (WO) cache architecture that reduces energy consumption in the L1 data cache. Observing that write operations are very likely to be merged in the write buffer because of their high localities, we construct the proposed WO cache architecture to utilize two schemes. First, the write operations update the write buffer but not the L1 data cache, which is updated later by the write buffer after the write operations are merged. Write merging significantly reduces write accesses to the data cache and, consequently, energy consumption. Second, we further reduce energy consumption in the write buffer by filtering out unnecessary read accesses to the write buffer using a read hit predictor. In this paper, we show that the proposed WO cache architecture is applicable to the conventional embedded processors that support both write-through and write-back policies. Further, the experimental results verify that the proposed cache architecture reduces energy consumption in data caches up to 14%.

Plugging Versus Logging

A promising technique to improve the write performance of solid-state disks (SSDs) is to use a disk write buffer. The goals of a write buffer is not only to reduce the write traffic to the flash chips but also to convert host write patterns into long and sequential write bursts. This study proposes a new buffer design consisting of a replacement policy and a write-back policy. The buffer monitors how the host workload stresses the flash translation layer upon garbage collection. This is used to dynamically adjust its replacement and write-back strategies for a good balance between write sequentiality and write randomness. When the garbage collection overhead is low, the write buffer favors high write sequentiality over low write randomness. When the flash translation layer observes a high overhead of garbage collection, the write buffer favors low write randomness over high write sequentiality. The proposed buffer design outperformed existing approaches by up to 20% under various workloads and flash translation algorithms, as will be shown in experiment results.

Cache Performance Optimization for SoC Vedio Applications

Chip Multiprocessors (CMPs) are adopted by industry to deal with the speed limit of the single-processor. But memory access has become the bottleneck of the performance, especially in multimedia applications. In this paper, a set of management policies is proposed to improve the cache performance for a SoC platform of video application. By analyzing the behavior of Vedio Engine, the memory-friendly writeback and efficient prefetch policies are adopted. The experiment platform is simulated by System C with ARM Cotex-A9 processor model. Experimental study shows that the performance can be improved by the proposed mechanism in contrast to the general cache without Last Level Cache (LLC): up to 18.87% Hit Rate increased, 10.62% MM Latency and 46.43% CPU Read Latency decreased for VENC/16way/64bytes; up to 52.1% Hit Rate increased, 11.43% MM Latency and 47.48% CPU Read Latency decreased for VDEC/16way/64bytes, but with only 8.62% and 4.23% Bandwidth increased respectively

캐시 버퍼와 읽기 요청을 고려한 낸드 플래시 기반 솔리드 스테이트 디스크의 요청 스케줄링 기법

솔리드 스테이트 디스크 (SSD)는 고성능 개인용 컴퓨터나 서버 분야에서 뛰어난 특성과 성능을 바탕으로 입지를 넓혀 나가고 있다. 특히 낸드 플래시 메모리에 기반한 SSD가 주류를 이루며 이미 거대한 시장을 확보하고 있는 낸드 플래시 메모리 시장의 큰 부분을 차지하고 있다. 이러한 낸드 플래시 메모리 기반 SSD에는 보통 낸드 플래시 메모리의 특성을 숨기기 위하여 DRAM으로 제작되는 캐시 버퍼가 장착되는데 이 캐시 버퍼는 보다 높은 성능을 달성하기 위해 나중 쓰기 방식을 활용하고 이는 기존의 낸드 플래시 메모리 만을 고려한 스케줄링 기법들을 I/F에서 효과적으로 활용할 수 없게 한다. 따라서 본 논문에서는 I/F에서 사용할 수 있는 캐시 버퍼를 고려한 스케줄링 기법을 제안하고자 한다. 스케줄링 기법은 크게 두 가지 기준을 가지고 스케줄링을 진행하는데 캐시 버퍼의 적중 여부와 읽기 요청에 대한 우선순위이다. 이는 캐시 버퍼에 적중한 요청들을 먼저 처리하여 처리속도를 증가시키고 시스템 성능에 보다 큰 영향을 끼치는 읽기 요청의 지연시간을 줄이기 위함이다. 실험 결과에 따르면 제안하는 스케줄링 기법을 사용했을 때 약 26% 향상된 읽기 성능을 보여주었다.

TESA: a temporal and spatial information aware writeback policy for home network-attached storage devices

Home Network-Attached Storage (NAS) provides an easy way for data sharing and backup among multiple consumer electronic devices in home networks. Because of large capacity and cost effectiveness, disks are widely adopted in home NAS devices. In addition, data writes are common for many home NAS devices since these devices are usually used for data storage and backup. A writeback policy selects which dirty buffers are to be flushed to the disk, which is critical to the system performance under write-intensive workloads. In this paper, an intelligent writeback policy for home NAS called TESA is proposed. In contrast to most existing writeback policies, TESA considers both temporal and spatial information of the dirty buffers to improve the writeback performance. Considering the temporal information helps to reduce the frequency of writing back recently used dirty buffers, and hence leads to reduced write traffic. Considering the spatial information causes a reduction in the overall seek time and rotation delay of the dirty buffer writeback. The TESA writeback policy was implemented on a NAS evaluation board running Linux kernel. The performance results shows that TESA yields a significant performance improvement (i.e., up to 33.1%) over the original writeback policy of Linux. Moreover, TESA outperforms the policy that considers only the temporal information of the dirty buffers by up to 21.0%, and it also has up to 10.9% performance improvement over a previous policy that considers both the temporal and spatial information.

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches

SRAM and DRAM have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology (eDRAM), thus overcoming the speed limit of typical DRAM cells. In this paper, we propose a hybrid n-bit macrocell that implements one SRAM cell and n-1 eDRAM cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Architectural mechanisms (e.g., special writeback policies) have been devised to completely avoid refresh logic. Performance, energy, and area have been analyzed in detail. Experimental results show that using typical eDRAM capacitors, and compared to a conventional cache, a 4-way set-associative hybrid cache reduces both energy consumption and area up to 54 and 29 percent, respectively, while having negligible impact on performance (less than 2 percent).

Implementation and Evaluation of File Write-Back and Prefetching for MPI-IO Over GPFS

In this paper we present the implementation of an open-source MPI-IO interface for the General Parallel File System (GPFS). Our solution includes the design and implementation of GPFS-based write-back and prefetching modules, which have been integrated in ROMIO. A collective file write strategy based on GPFS data-shipping, and a view-based collective I/O mechanism, relying on GPFS mechanisms, are at the core of the novel optimizations proposed in this paper. View-based collective I/O includes a thread-based flushing method implementing a write-back policy for latency hiding, and a prefetching method, based on GPFS hints, to increase small read access performance. Performance evaluations show that our implementation achieves high-performance and hides the latency of file accesses through the combination of view-based collective file accesses, and the overlapping of computation, communication and I/O. This is especially true for collective and small-size access patterns, which are very frequent in parallel scientific applications.

Using Write Mask to Support Hybrid Write-Back and Write-Through Cache Policy on Many-Core Architectures

Write-back cache policy can greatly save bandwidth consumption for write operations.It′s particularly beneficial in many-core architecture.Normally CMP uses write-invalid or write-update cache protocol like directory based MESI which is hardly scalable and too complex.Alternatively the authors implemented scope consistency(and lock-based cache coherence protocol) on chip,add write-mask for each cacheline of L1 Dcache to record the written byte′s location and solve the false sharing problem.To further optimize the write-mask storage overhead,two methods are proposed.First the authors set store instructions with 1/2/3 bytes write-through property and let every 4-byte data has 1 bit write-mask.This method can compress the chip area of write-mask to 27.9% of origin byte-grain design.Secondly they design write mask buffer whose entry counts 12.5% of total number of Dcache blocks and compress the area overhead to 17.7% of origin without performance lost.On Godson-T 64-core platform which uses scope consistency,they use write-mask to implement hybrid WB/WT cache policy(in the scope range with possible data race we implement write-through,but out of the scope range without data race they choose write-back).Three splash2 programs and two biological programs are evaluate.The results show that performance improvement is above 24% compared to completely write-through and no performance lost under the two storage optimizations.

Dusty caches for reference counting garbage collection

Reference counting is a garbage-collection technique that maintains a per-object count of the number of pointers to that object. When the count reaches zero, the object must be dead and can be collected. Although it is cannot detect all garbage on its own, it is well suited for some applications and is implemented typically in conjunction with other methods to increase overall precision. A disadvantage of reference counting is the extra storage traffic that is introduced. In this paper, we describe a new cache write-back policy that can substantially decrease the reference-counting traffic to RAM.We investigate a cache design that takes advantage of temporally silent stores, by remebering the first-fetched value of a cache subblock, so that the subblock need not be written back to RAM unless a different value is present. We present results from experiments that show the effectiveness of this approach, particularly in mitigating the storage traffic due to reference counting.

An Analytic Study of Caching in Computer Systems

Cache performance is analyzed for the independent reference model (IRM) of data reference in conjunction with the least recently used (LRU) cache block replacement policy. The method has low computational complexity and high accuracy. The method computes the cache-hit rate, the probabilities of various numbers of references to a block while it is cache resident, the probabilities a block being replaced belongs to each memory segment (grouping by probability of access), the probability that a block being replaced was modified while in cache (assuming write-back policy), and the average number of references made to all blocks since the last reference to a block being replaced. The analysis is extended to address cache coherence in parallel and distributed systems.

Performance analysis of disk cache write policies

Many different techniques for bridging the performance gap between CPUs and I O devices have been studied. Among these is data caching at the disk controller. Of interest is the effectiveness of a disk cache under the presence of a higher level cache, such as the UNIX file buffer cache. Disk activity logs from a UNIX workstation file server have been collected and analysed. Results have been used to guide the design of disk cache architectures, which are analysed using simulations driven by the activity logs. The primary focus is on disk cache write strategies. It is shown that write-through policies achieve the best read response time, with a 4MB cache performing approximately 30% better than no cache. Write-back policies do not achieve the performance of write-through policies (nor even the performance of a system with no disk cache) due to a phenomenon referred to as ‘head thrashing’. Scheduled write-back, a new write policy that utilizes disk idle time to write dirty lines from the cache efficiently, is examined as a solution to the problem and is shown to achieve performance equivalent to that of write-through under light to moderate loads. A variation of the pure LRU replacement algorithm, LRU over clean lines, is proposed for use with scheduled write-back, and is shown to achieve read response times significantly less than pure write-through under simulated heavier loads.

Performance benefits of non‐volatile caches in distributed file systems

AbstractWe study the use of non‐volatile memory for caching in distributed file systems. This provides an advantage over traditional distributed file systems in that the load is reduced at the server without making the data vulnerable to failures. We propose the use of a small non‐volatile cache for writes, at the client and the file server, together with a larger volatile read cache to keep the cost of the caches reasonable.We use a synthetic workload developed from analysis of file I/O traces from commercial production systems and use a detailed simulation of the distributed environment. The service times for the resources of the system were derived from measurements performed on a typical workstation.We show that non‐volatile write caches at the clients and the file server reduce the write response time and the load on the file server dramatically, thus improving the scalability of the system. We examine the comparative benefits of two alternative writeback policies for the non‐volatile write cache. We show that a proposed threshold based writeback policy is more effective than a periodic writeback policy under heavy load. We also investigate the effect of varying the write cache size and show that introducing a small non‐volatile cache at the client in conjunction with a moderate sized non‐volatile server write cache improves the write response time by a factor of four at all load levels.

Caching and Writeback Policies in Parallel File Systems

Improvements in the processing speed of multiprocessors are outpacing improvements in the speed of disk hardware. Parallel disk I/O subsystems have been proposed as one way to close the gap between processor and disk speeds. Such parallel disk systems require parallel file system software to avoid performance-limiting bottlenecks. We discuss cache management techniques that can be used in a parallel file system implementation for multiprocessors with scientific workloads. We examine several write-back policies, and give results of experiments that test their performance.

A study of I/O system organizations

With the increasing processing speeds, it has become important to design powerful and efficient I/O systems. In this paper, we look at several design options in designing an I/O system and study their impact on the performance. Specifically, we use trace driven simulations to study a disk system with a nonvolatile cache. Some of the considered design parameters include the cache block size, the fetch size, the cache size and the disk access policy. We show that decoupling the fetch size and the cache block size results in significant performance improvements. A new write-back policy is presented that is shown to offer significant performance benefits. We show that optimal block size in a two-level memory hierarchy is dependent only on the latency, data rate product of the second level as previously conjectured. We also present results showing the effect of a split access operation of a disk read/write head.