Write Power Dissipation Research Articles

Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.

Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( $$\sim $$ ~ 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage $$V_\mathrm{L}$$ V L ( $$\sim $$ ~ 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ $$V_\mathrm{DD})^{ 2 }\,\times $$ V DD ) 2 × 100 %) due to reduced voltage swing (from $$V_\mathrm{DD }$$ V DD = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a $$256 \times 64$$ 256 × 64 bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.

Enhancing Leakage Power in CPU Cache Using Inverted Architecture

Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power so power and energy consumption parameters have become one of the most important design constraint. It is one of the most attractive targets for power reduction. This paper presents an approach to enhance the dynamic power consumption of CPU cache using inverted cache architecture. Our assumption tries to reduce dynamic write power dissipation based on number of ones and zeros in the in-coming cache block data using bit to indicate is the block is mostly one or zero. This architecture reduces the dynamic write power by 17 %. We use Proteus Simulator to test that proposed circuit and performed the experiments on a modified version of the cacti6.0 simulator.

A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells

The use of multiple power supplies with different output voltages has a great advantage in that it makes it possible to realize high performance ULSIs with low power dissipation. This paper presents a high-speed low-power SRAM that employs three power supplies (1, 2, and 3.3 V). A 1-V power supply is mainly used in the SRAM core to save standby and/or active power, while a 2-V supply is used in critical components to realize high performance. The voltage applicable to each MOSFET is up to 2.2 V because of the use of a 5-nm ultrathin gate oxide, and so the 3.3-V power supply is used only for LV-TTL level I/O buffers. Secure write operation for 1-V six-transistor memory cells is guaranteed by using a new switched powerline impedance scheme. To reduce dynamic write power dissipation, a segmented bitline scheme is adopted and long global bitlines are assigned to the 4th (topmost) metal layer. The data stored in memory cells are read out via virtual-GND lines by sensing the change in current volume. The practical use of parasitic bipolar action in SOI MOSFETs is being actively considered as a way of obtaining a large read current from memory cells. In addition, a 1-V double-rail bidirectional intradatabus is developed for transferring multibit high-speed data between the SRAM core and I/O buffers. A 32K-word × 9-bit SRAM chip, fabricated with the 0.2-μm-gate CMOS/SIMOX process, has achieved a 7.5-ns address access time for 65-pF external loads. The power dissipation during standby is less than 0.3 mW and the values for 100-MHz operation are 5.8 mW (write) and 11.0 mW (read), excluding that of the 3.3-V I/O buffers.

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Delayed relaxation in thin-film heads

The delayed relaxation after writing with a Permalloy thin-film head has been studied experimentally. The phenomenon of delayed relaxation is shown to be caused predominantly by stress-induced relaxation of the flux closure domains along the edges of the thin-film-head yoke. It is necessary for this effect that the composition of the Permalloy yields nonzero magnetostriction. The fairly rapid temperature change directly after write will then trigger irreversible wall displacements which show up as transient noise pulses in the head output. Depending on the actual edge domain relaxation, these transients can have a positive or a negative polarity, or can be bipolarity transients. This thermomechanically triggered irreversible wall-motion process can fairly accurately be modeled as a Poisson process. The model predicts the arrival time distribution, the probability of occurrence for different write currents, and threshold settings reasonably well. This 'noise-after-write' effect can be made smaller by striving for zero magnetostriction and a lower write power dissipation, and to some extent by increasing the thermal conductivity to the slider.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>