Worst-case Power Consumption Research Articles

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Worst Case Execution Time and Power Estimation of Multicore and GPU Software: A Pedestrian Detection Use Case

Worst Case Execution Time estimation of software running on parallel platforms is a challenging task, due to resource interference of other tasks and the complexity of the underlying CPU and GPU hardware architectures. Similarly, the increased complexity of the hardware, challenges the estimation of worst case power consumption. In this paper, we employ Measurement Based Probabilistic Timing Analysis (MBPTA), which is capable of managing complex architectures such as multicores. We enable its use by software randomisation, which we show for the first time that is also possible on GPUs. We demonstrate our method on a pedestrian detection use case on an embedded multicore and GPU platform for the automotive domain, the NVIDIA Xavier. Moreover, we extend our measurement based probabilistic method in order to predict the worst case power consumption of the software on the same platform.

DynGATT: A dynamic GATT-based data synchronization protocol for BLE networks

Bluetooth Low Energy (BLE) is a wireless communication technology for power-constrained Internet of Things (IoT) applications. BLE data can be transmitted via either the IPv6 or the Generic ATTribute (GATT) Profile protocol, with the former supporting dynamic IoT structures and the latter being application-friendly. In fact, GATT requires the data layout to be known in advance by peer devices, in order to properly interpret the received data. In this paper, we introduce DynGATT, a protocol that achieves the benefits of both IPv6 and GATT, by extending GATT in a seamless fashion to support dynamic IoT structures. The key idea of DynGATT is to use GATT descriptors, originally intended to specify data in static IoT scenarios, to also specify IoT systems whose structures may dynamically evolve. Peer devices reading these descriptors will know how to interpret the data of GATT characteristics provided by devices joining the IoT network. Because no additional data have to be transmitted, the connection time is then reduced with respect to classical BLE. DynGATT has been implemented and tested in an agricultural IoT application, with different types of sensor nodes. Our experimental evaluation shows that DynGATT is very power-efficient, despite its added flexibility. Its worst-case power consumption is only around 19.37µA per data transmission and around 41.37µA overall. This consumption can be further reduced by using the methods discussed in this paper. To the best of our knowledge, this work is the first to support dynamic IoT structures in a GATT-based setting.

A Sub-1 V Bulk-Driven Rail to Rail Dynamic Voltage Comparator with Enhanced Transconductance

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.

Analytical Program Power Characterization for Battery Depletion-time Estimation

Appropriate battery selection is a major design decision regarding the fast growth of battery-operated devices like space rovers, wireless sensor network nodes, rescue robots, and so on. Many such systems are mission critical, where estimation of the battery depletion time has an important role in the design efficiency with regard to the mission time. Accurate characterization of the system power usage pattern is essential for such an estimation. The following complexities exist: (1) The system behavior changes during interaction with the physical world, (2) the power consumption varies as the runtime progresses, (3) the total delivered battery charge has non-linear dependency on the power variability, and (4) design-time exhaustive study about runtime execution paths is almost impossible. This article presents an analytical method to first characterize the power variability of a given embedded program modeled by a directed acyclic graph, concerning the first and the second complexities. To include the third complexity, however, the concept of Worst-case Power Consumption Trace (WPCT) is proposed toward the worst-case scenario in terms of charge depletion for a given battery. A polynomial algorithm is also presented to construct WPCT and use it to estimate a tight lower bound for the system energy depletion time, i.e., its failure time, avoiding an exhaustive study. Comparisons between the analytical and simulation results reveal less than 3.4% of error in the bound estimations for the considered setups.

Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-$\mu$ W Keyword Spotting and Speaker Verification

The use of speech-triggered wake-up interfaces has grown significantly in the last few years for use in ubiquitous and mobile devices. Since these interfaces must always be active, power consumption is one of their primary design metrics. This article presents a complete mixed-signal system-on-chip, capable of directly interfacing to an analog microphone and performing keyword spotting (KWS) and speaker verification (SV), without any need for further external accesses. Through the use of: 1) an integrated single-chip digital-friendly design; b) hardware-aware algorithmic optimization; and c) memory- and power-optimized accelerators, ultra-low power is achieved while maintaining high accuracy for speech recognition tasks. The 65-nm implementation achieves 18.3- $\mu \text{W}$ worst case power consumption or 10.6- $\mu \text{W}$ power for typical real-time scenarios, $10\times $ below state of the art (SoA).

Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.

What Your DRAM Power Models Are Not Telling You

Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided by DRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate when compared with the real power consumed by DRAM. This is because existing DRAM power models (1) are based off of the worst-case power consumption of devices, as vendor specifications list the current consumed by the most power-hungry device sold; (2) do not capture variations in DRAM power consumption due to different data value patterns; and (3) do not account for any variation across different devices or within a device.

Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers

Synchronous dynamic random access memories (SDRAMs) are widely employed in multi- and many-core platforms due to their high-density and low-cost. Nevertheless, their benefits come at the price of a complex two-stage access protocol, which reflects their bank-based structure and an internal level of explicitly managed caching. In scenarios in which requestors demand real-time guarantees, these features pose a predictability challenge and, in order to tackle it, several SDRAM controllers have been proposed. In this context, recent research shows that a combination of bank privatization and open-row policy (exploiting the caching over the boundary of a single request) represents an effective way to tackle the problem. However, such approach uncovered a new challenge: the data bus turnaround overhead. In SDRAMs, a single data bus is shared by read and write operations. Alternating read and write operations is, consequently, highly undesirable, as the data bus must remain idle during a turnaround. Therefore, in this article, we propose a SDRAM controller that reorders read and write commands, which minimizes data bus turnarounds. Moreover, we compare our approach analytically and experimentally with existing real-time SDRAM controllers both from the worst-case latency and power consumption perspectives.

A sub 125 nW sub-threshold analog adaptive sampler in 180 nm CMOS.

We present an ultra low power analogue adaptive sampler for extraction of features from an arterial blood pressure signal, prior to ADC operation or conversion. The architecture is implemented and simulated in UMC 180 nm technology. A worst case power consumption across process variation of 124.6 nW was achieved, with a process invariant key-point timing error of approximately 2.31 ms, corresponding to a sample error of magnitude less than 0.1 mmHg, simulated at body temperature of 37°C. This is significantly below the standard clinical recording accuracy of 1 mmHg for electronic measurement tools.

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options.

Distributed consolidation of virtual machines for power efficiency in heterogeneous cloud data centers

Data centers use dynamic virtual machine consolidation to reduce power consumption. Existing consolidation mechanisms are not efficient in cloud data centers, which have heterogeneous hardware infrastructure, huge scale, and highly variable non-stationary workloads. We use game theory to develop a novel distributed mechanism for both heterogeneous and homogeneous data centers of cloud computing. Our mathematical analysis shows that our mechanism converges after a finite number of migrations. In addition, we show that our worst case power consumption is only 23% more than the theoretical minimum. In order to validate our claim, we preform simulation in CloudSim with real workload traces from Google data centers.

Compiler-Directed Power Management for Superscalars

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip

Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cores on a single chip. With the development of silicon photonics for short-haul optical communication, wavelength division multiplexing (WDM)-based optical networks-on-chip (ONoCs) are emerging on-chip communication architectures that can potentially offer high bandwidth and power efficiency. Thermal sensitivity of photonic devices is one of the main concerns about the on-chip optical interconnects. We systematically modeled thermal effects in optical links in WDM-based ONoCs. Based on the proposed thermal models, we developed OTemp, an optical thermal effect modeling platform for optical links in both WDM-based ONoCs and single-wavelength ONoCs. OTemp can be used to simulate the power consumption as well as optical power loss for optical links under temperature variations. We use case studies to quantitatively analyze the worst-case power consumption for one wavelength in an eight-wavelength WDM-based optical link under different configurations of low-temperature-dependence techniques. Results show that the worst-case power consumption increases dramatically with on-chip temperature variations. Thermal-based adjustment and optimal device settings can help reduce power consumption under temperature variations. Assume that off-chip vertical-cavity surface-emitting lasers are used as the laser source with WDM channel spacing of 1 nm, if we use thermal-based adjustment with guard rings for channel remapping, the worst-case total power consumption is 6.7 pJ/bit under the maximum temperature variation of 60 °C; larger channel spacing would result in a larger worst-case power consumption in this case. If we use thermal-based adjustment without channel remapping, the worst-case total power consumption is around 9.8 pJ/bit under the maximum temperature variation of 60 °C; in this case, the worst-case power consumption would benefit from a larger channel spacing.

Low-power design in aerospace circuits: A case study

The results of applying low-power design techniques to a circuit used in a space application have been presented. The design used for the experiments was implemented in an antifuse FPGA (ACTEL RT14100A). Power consumption was first estimated by simulation of the design to identify the elements that had a higher impact on the total power consumption. According to the power estimations, the more suitable power reduction techniques were identified and applied to reduce power consumption of the initial design. With this approach, the worst-case power consumption was reduced to 30% of the original power estimations by using gated clocks and redesigning small critical components with an asynchronous style. Further reduction, typically up to 16% of the original value, was possible by applying architectural modifications. These results show that important power savings are possible for FPGA designs by following the appropriate methodology. Precise estimation of the contribution of the various functional units to the total power is essential to target only those modifications that are significant from the power point of view and to avoid large redesign efforts.

Data Structure Optimization for Power- Efficient IP Lookup Architectures

Power consumption has become a limiting factor in designing next generation network routers. Recent observation shows that IP lookup engines dominate the power consumption of core routers. Previous work on reducing power consumption of routers mainly focused on network- and system-level optimizations. This paper represents the first thorough study on the data structure optimization for lowering the power consumption in static random access memory (SRAM)-based IP lookup engines. Three different SRAM-based IP lookup architectures are discussed: nonpipelined, simple pipelined, and memory-balanced pipelined architectures. For each architecture, we formulate the problem of power minimization by revisiting the time-space tradeoff in multibit tries. Two distinct multibit trie algorithms are investigated: the expanded trie and the tree bitmap trie, which are widely used in SRAM-based IP lookup solutions. A theoretical framework is proposed to determine the optimal strides for building a multibit trie so that the worst-case power consumption of the IP lookup architecture is minimized. Experiments using real-life routing tables including both IPv4 and IPv6 data sets demonstrate that careful selection of strides in building the multibit tries can reduce the power consumption dramatically. We believe our methodology can be applied to other variants of multibit tries and can help in designing more power-efficient SRAM-based IP lookup architectures.

Power Aware IP Lookup Architecture and Algorithm for Green Router

With the development of next generation network which used Ipv6 technology, recent routers architecture meet many questions in performance, complexity and power consumption. With the expanding of network scale, how to implement a low power and MSF for IP lookup is a challenge in green high-powered router design. This paper represents a FIB multi-level mapping routing lookup architecture FMML, the dynamic routing table mapping algorithm is designed to determine the optimal strides for building tree bitmap tries so that the worst-case power consumption of the IP lookup engine is minimized. Experiments using real-life routing tables demonstrate that careful design of the data structure can reduce the power consumption dramatically.

Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator

The authors propose a ring-based injection-locked frequency divider (ILFD) incorporating a novel process and temperature compensation technique. The core of the ILFD consists of a process and temperature compensated ring oscillator based on modified symmetric load delay elements. Measurement results show that the natural frequency of oscillation of the ring oscillator varies only 4.4% across six different chips and for a temperature range of 0–80°C. The ILFD possesses a wide locking range over process corners as well as a wide temperature range because of the proposed compensation technique and the incorporation of the delay cell architecture in the design. A calibration circuitry can be used to further enhance the locking range. Measurement results show that the proposed ILFD functions as a divide-by-4 for an input frequency range of 1.8–3.2 GHz for an input power level as low as −3 dBm. The worst-case power consumption was approximately 2 mW from a 1.8 V power supply. The proposed ILFD can be used as a low-power prescaler for multi-band applications.

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

Boolean satisfiability (SAT) is a core non polynomial (NP)-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. The authors present a hardware solution to the SAT problem. They propose a custom integrated circuit (IC) to implement their approach, in which the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. Further, extracting the minimum unsatisfiable core (i.e. the formula consisting of the smallest set of clauses of the initial formula which is unsatisfiable) is also a computationally hard problem. The proposed hardware approach, in addition to solving SAT, efficiently extracts the minimum unsatisfiable core for any unsatisfiable formula. To the best of the authors' knowledge, this is the first hardware-based solution proposed for extracting the unsatisfiable core. In this approach, clause literals are stored in specially designed clause cells. Clauses are implemented in banks, in a manner that allows clauses of variable width to be accommodated in these banks. To maximise the utilisation of these banks, the authors initially partition the SAT problem. Their solution has significantly larger capacity than existing hardware SAT solvers, and is scalable in the sense that several ICs can be used to simultaneously operate on the same SAT instance. The area, power and performance figures are derived from layout and SPICE (using extracted parasitics) estimates. The approach presented has been functionally validated in Verilog. Preliminary results demonstrate that the approach can accommodate instances with approximately 63 K clauses on a single IC of size 1.5 cm×1.5 cm. This hardware based-SAT solving approach results in over three orders of magnitude speed improvement over Boolean constraint propogation-based software SAT approaches (one to two orders of magnitude over other hardware SAT approaches). The capacity of this approach is significantly higher than most hardware-based approaches. Further, the worst case power consumption was found to be ≤1 mW for the implementation.

A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range

A third-order G/sub m/-C Butterworth low-pass filter implementing G/sub m/-tuning and G/sub m/-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its G/sub m/-switching feature allows extending the tuning range and adapting the power consumption. The filter's cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBV/sub p/ is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm/sup 2/ in a 0.25-/spl mu/m SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range.