Wide Range Of Supply Voltages Research Articles

An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs

Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications

This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM’s retention time. The implementation of a homogeneous NMOS-based 2T gain cell not only reduces write access times but also benefits from a boosted write wordline technique. In a comparison with the previous pseudo-static gain cell design, the proposed PS-nGC exhibits improvements in write and read access times, achieving 3.27 times and 1.81 times reductions in write access time and read access time, respectively. Furthermore, the PS-nGC demonstrates versatility by accommodating a wide supply voltage range, spanning from 0.7 to 1.2 V, while maintaining an operating frequency of 667 MHz. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the prototype features an efficient active area, occupying a mere 0.284 µm2 per bitcell for the 4 kb eDRAM macro. Under various operational conditions, including different processes, voltages, and temperatures, the proposed PS-nGC of eDRAM consistently provides speedy and reliable read and write operations.

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This paper proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380 fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

Design of High Precision Temperature Sensor with Current Gain Compensation Technology for On-Chip Application

The integration of on-chip temperature sensors within various systems, industrial Internet of Things (IoT), and wireless sensor networks is greatly facilitated by their small size, cost-effectiveness, and capability to provide direct digital output. However, the diverse application scenarios pose challenges in designing these sensors. On one hand, real-time clock calibration demands high-precision temperature sensors, while on-chip heat management emphasizes compactness and low-voltage operation. Additionally, streamlining the calibration cost for mass production holds significant practical value. Addressing these challenges, this study systematically investigates on-chip complementary metal-oxide-semiconductor (CMOS) temperature sensors based on distinct signal domains processed by temperature readout circuits. Specifically, the research commences by analyzing the issues of several degeneracy points in the front-end circuit of a bipolar junction transistor (BJT) temperature sensor with current gain compensation technology. To address the intricate design challenges in advanced technologies and calibration complexities in industrial applications, dynamic component matching, current gain compensation, and chopper stabilization are harnessed. A novel dynamic current gain canceling technique for temperature readout is introduced, enhancing temperature measurement accuracy without incurring additional power consumption or area overhead. Ultimately, an all-digital CMOS temperature sensor is realized using the SMIC 55 nm CMOS process. Occupying a mere 0.29 mm2 of core area, the design operates efficiently across a wide supply voltage range of 1.2 V to 3.6 V. Covering a temperature spectrum from −40 °C to 125 °C, the sensor demonstrates a calibration error of just ±0.7 °C. This achievement is attributed to the incorporation of the proposed dynamic current gain compensation technique.

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi-or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a 2 × 2 2D mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables 1.4×, 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by 200× and increase throughput by 19.9% for the NoC at 0.4 V, 25∘C.

The Design of Digital System with CSA

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and ORAND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

An all-digital CMOS temperature sensor with a wide supply voltage range

This paper proposes a MOSFET-based all-digital temperature sensor fabricated in a standard 55-nm CMOS process. The temperature sensing elements of the sensor are composed of ring oscillators, which convert temperature information into frequency information. The frequency ratio’s proportional to absolute temperature (PTAT) feature is generated by using two separate frequency oscillators with varied temperature sensitivity. The frequency-to-digital converter (FDC) converts frequency information into digital representation without introducing any overhead reference clock. A die area of 1915µm2 is occupied, owing to the all-digital architecture. After two-point calibration, the proposed sensor achieves an error of -0.4°C∼+0.6°C throughout a temperature range of -40°C∼125°C. With the help of class-adjustable oscillators, the sensor can function in a wide supply voltage range from 0.5V to 1.2V. It obtains a resolution of 0.166°C at room temperature with a dissipation of 2.5µW.

Vectron as an Example of a Modern and Versatile Electric and Diesel Locomotive for Passenger and Freight Transport

The Vectron locomotives are a Siemens proposal covering locomotives dedicated to both passenger and freight traffic, capable of operating under a wide range of supply voltages (multi-system, single-system, etc. versions are offered), on both normal and broad-gauge track. A diesel version was also designed for operation on non-electrified lines. The Vectron locomotives are a variant of the Eurosprinter ones, developed in the early 1990s and enriched by the operation experience acquired, both on the German or Austrian railway network and in other EU countries (acceptance to operate as part of the liberalization of the common market). To date, circa 1,500 Eurosprinter locomotives have been sold, primarily in Europe and also in the USA, where they are operated in moderate climate, and both the Mediterranean one and the cold Scandinavian winters. Keywords: electric locomotives, multisystem voltage locomotives, Vectron, Siemens

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

AbstractA 1 nA current reference circuit is designed in semiconductor laboratory (SCL) 0.18 μm standard threshold voltage CMOS technology under 1.8 V power supply. The reference current is extremely immune to supply variation and shows a line sensitivity of 0.002%/V at post layout simulation level, over a wide range of supply variation from 0.5 V to 3.5 V. The line sensitivity is much smaller than any relevant data so far reported. In addition, it has a very low temperature coefficient of 214 ppm/°C over a temperature variation from −50°C to 50°C. The circuit consumes a total power of 588 nW. The reported results are also studied at various process corners and under variable process parameters like oxide thickness and threshold voltage of transistors. A satisfactory behaviour of the circuit is obtained in all cases. The accuracy of the simulation results is validated through quite close matching of the results with that obtained through rigorously developed theoretical models.

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm2 and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.

Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs

This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. The proposed circuit addresses three major LDO design challenges: frequency compensation for a wide range of output currents and load capacitors, fast response to load transients and reduced sensitivity to the supply variations. It was used to implement an LDO that provides a 5V output voltage and up to 50mA output current over a wide range of supply voltages &#x2013; from 5.25V to 40V &#x2013; and temperatures, &#x2212;40^oC to &#x002B;150^oC, while burning as little as <inline-formula> <tex-math notation="LaTeX">$30\mu \text{A}$ </tex-math></inline-formula>. The slew-rate booster ensures that the output voltage overshoot and undershoot caused by load jumps of 50mA/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> remain below 4&#x0025; of the nominal Vout value. Moreover, the LDO meets the E-06 test requirements within the LV124 automotive standard: the output voltage varies within 10&#x0025; of its nominal value when sinusoidal voltages with amplitudes up to 20V peak-to-peak and frequency varying between 15Hz and 100kHz are injected into the LDO supply line. This feature is achieved while using a capacitor of only <inline-formula> <tex-math notation="LaTeX">$1\mu \text{F}$ </tex-math></inline-formula> at the output, up to 10 times smaller than the decoupling capacitors used by similar LDOs reported previously.

A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> with the proposed ESS scheme applied.

A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS

Strong physically unclonable function (PUF) offers a promising solution to low-cost hardware identification and authentication for Internet of Things (IoT) applications. The continuous advancement of machine learning (ML) technology makes the PUF resilience to ML attacks a major design priority. This paper presents a robust and area-efficient strong PUF design with high ML attack resilience. The proposed PUF architecture based on inverter amplifiers operating in the subthreshold region achieves both low energy consumption and high supply and temperature scalability. The proposed nonlinearity topology effectively enhances PUF resilience to various ML attacks with low implementation area and cost. The proposed strong PUF design was designed and implemented using a 28-nm CMOS process. The measurement results show that the proposed PUF design achieves a nearly ideal ML attack resilience of 49.96 &#x0025; with a small area of 239,857 F², and demonstrates a stable operation across a wide range of supply voltage from 0.5&#x2013;1.4 V and temperature from &#x2212;40&#x2013;100 &#x00B0;C. This represents <inline-formula> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> improvement in area efficiency, <inline-formula> <tex-math notation="LaTeX">$2.25\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.08\times $ </tex-math></inline-formula> improvement in operating voltage and temperature range, respectively, compared to the state-of-the-art results.

A 42nA IQ , 1.5–6V VIN , Self-Regulated CMOS Voltage Reference With −93dB PSR at 10 Hz for Energy Harvesting Systems

This brief proposes a low-power voltage reference with low line sensitivity and high power supply rejection (PSR) under relatively wide supply voltage range. Excluding the small capacitors in start-up circuits, the proposed voltage reference is composed of only MOSFETs, most of which have been biased into the subthreshold region to achieve low power consumption. The self-regulating technique was also adopted to suppress the supply ripples and stabilize the supply voltage for the core reference circuits. The proposed reference circuit has been fabricated in 0.18- μm CMOS technology with a total chip area of 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When supply voltage is 1.5 V, the measured reference voltage is 985 mV and the total quiescent current is 42 nA. The measured temperature coefficient (TC) from -40°C to 85°C is 60.86 ppm/°C, while the line sensitivity is as low as 0.003 %/V over 1.5 ~ 6V supply range. Besides, the measured PSR is -93 dB and -57 dB, at 10 Hz and 1 MHz, respectively.

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP.

Power Factor Preregulation in Interleaved Luo Converter-Fed Electric Vehicle Battery Charger

This work deals with the design and implementation of a new interleaved Luo power factor preregulator (PFP)-based electric vehicle (EV) battery charger, which is suitable for low-cost and improved power quality (PQ)-based EV charging. By interleaving two Luo converter cells, the input current is divided between them, which provides reliable and efficient charging of the battery at high-power discontinuous conduction mode (DCM) operation. This reduces the switch conduction loss due to reduced device current stress and thus, the charger efficiency is improved. The interleaved Luo converter incorporates low input and output current ripple due to ripple cancellation. This charger operates in constant current mode up to certain battery state of charge (SOC). However, for higher SOC range, it maintains constant voltage charging using a flyback converter at the next stage. Two converters are designed in DCM to provide inbuilt zero current switching and circuit diodes show good reverse recovery. An inherent PF preregulation is obtained at input mains over a wide range of supply voltages as well as dc-link voltage. The total harmonic distortion of input current is obtained as per PQ regulations. Its prototype is built and tested to validate its improved performance over two-stage solutions.

A Generalized Dynamic Conductance Model for High Intensity Discharge Lamps and its Prospective Application to Design Dimmable Electronic Ballast

A generalized model for high intensity discharge (HID) lamp is developed based on the Francis-Damelincourt dynamic conductance model of electric discharge by replacing the model constants A, B, C, D with four experimentally determined coefficient functions of rated lamp power and root mean square supply voltage. Experimental validation of this model is done, which shows a maximum deviation of about 5 %. Moreover, sensitivity analysis for the model coefficients is also performed, results of which conform to the physical behaviour of high pressure sodium (HPS) and metal halide (MH) lamps. This model is capable to simulate electrical characteristics of HPS and MH lamps of wide range of commercially available rated power (70–400) W fed by a wide range of supply voltage (180–250) V, 50 Hz. As a prospective application, the model is applied to design dimmable low frequency square wave electronic ballast for HID lamps. A design algorithm is proposed for this purpose. Performance analysis of the designed ballast is conducted in Matlab-Simulink environment, which shows fairly good performance of the circuit in terms of dimming accuracy (maximum deviation 2.64 %), lamp power factor (≥ 0.993), and lamp current crest factor (equal to 1.0). The model can also be utilized for designing electronic ballasts of other topologies.

Single-Event Latchup in a 7-nm Bulk FinFET Technology

Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> ) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat.

NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution

This article presents a fully integrated stand-alone narrowband Internet-of-Things (NB-IoT) and global navigation satellite system (GNSS) system-on-chip (SoC). It aims for an all-in-one system to integrate all necessary blocks such as an RF transceiver, a power management system (PMIP), and a clock management system and to save a bills-of-material (BOM) cost. An RF transceiver is integrated to support multi-band cellular IoT and GNSS with a CMOS RF power amplifier transmitting 23-dBm output power. A PMIP, including bucks, a boost, and low-dropout regulators (LDOs), is integrated to support coin cell or AAA battery and to support a wide input supply voltage range from 2.5 to 5 V. In addition, clock management system is embedded with a digitally controlled crystal oscillator (DCXO), a relaxation oscillator (RCO), and temperature sensor units (TSUs). It is fabricated in a standard 28-nm CMOS process and its size is 24.6 mm2. The power consumption of always-on-block is 15 $\mu \text{W}$ , and the sleep current consumption is less than 10 $\mu \text{A}$ at 3.8 V.

A 490-pW SAR Temperature Sensor With a Leakage-Based Bandgap-Vth Reference

This brief presents a temperature sensor that combines a leakage-based bandgap-Vth reference and an asynchronous SAR. The proposed sensor is implemented with 0.18 $\mu \text{m}$ CMOS technology. By sampling leakage-based biases directly in the SAR ADC, the sensor consumes 490 pW at 20 °C with a conversion time of 200 ms and stably works with a 1-point calibration, showing a ±2.35 °C peak-to-peak inaccuracy from −10 to 100 °C. The proposed sensor can operate across a wide range of supply voltage of 1 V to 2.1 V, with a supply sensitivity of 1.073 °C/V.