Wide-range Delay-locked Loop Research Articles

A low-power low-jitter DLL with a differential closed-loop duty cycle corrector

A low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential closed-loop structure that corrects the input clock duty cycle from 10 to 90%. To have a wide range DLL, a low-power voltage control delay line using wide bandwidth and large tuning range delay cells is employed. The proposed DLL has been fabricated in a 0.13 μm CMOS process technology with an active Si area of 0.11 mm2. The measured results show the DLL exhibits a lock range of 0.1–1.2 GHz while the peak-to peak jitter and rms jitter are 7.3 and 1.2 ps at 1.2 GHz, respectively. The total power dissipated by the DLL is 4.8 mW with 1.2 V supply voltage at 1.2 GHz.

Wide‐range harmonic lock detector with real‐time delay measurement of delay‐locked loop

A new robust harmonic lock detector (HLD) suitable for a wide-range delay-locked loop (DLL) is presented. This detector is composed of some delay indicators measuring the total delay of the DLL in real time, and it can detect the harmonic lock for a wide frequency range close to 1–20 times higher than the minimum frequency. Owing to its seamless operation without any initialising process using external reset control, it can ensure reliable lock detection despite some unusual conditions, such as frequency change, electrical surge input or power-ground fluctuation. The proposed HLD and the DLL were designed in 0.13 µm CMOS technology, and the simulation results showed the exact harmonic lock detection and reliable DLL locking properties over the whole frequency range from 25 to 500 MHz of the input clock.

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and duty cycle control is presented. A voltage-controlled sawtooth delay line provides not only the delay control but also duty cycle control. The proposed DLL achieves infinite phase shift by using a single loop. Therefore, it has the benefits of good jitter and wide range compared with the conventional dual-loop DLL. The proposed DLL has been fabricated in a 0.18-mum CMOS process and the core area is 0.45 times 0.3 mm2. The measurement results show the proposed DLL operates from 50 MHz to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured peak-to-peak jitter is 11.1 ps and the power consumption is 6 mW.

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs.

A 250-MHz-2-GHz wide-range delay-locked loop

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.

A reset-free anti-harmonic delay-locked loop using a cycle period detector

This paper describes a new delay-locked loop (DLL) circuit that uses a replica delay line and a cycle period detector to solve the false lock problem in the conventional DLLs. The auxiliary loop in the proposed DLL monitors the lock state of the main loop by estimating the cycle period of the input clock and decides whether the main loop is in the coarse lock state or not. The auxiliary loop does not require an external reset or a start-up signal for the coarse lock operation, which is performed in the background without affecting the fine lock operation of the main loop. The proposed DLL is useful in the applications such as wide range DLLs and multiphase clock generators. The proposed DLL was implemented in 0.25-/spl mu/m mixed-mode CMOS technology and its operating frequency ranges from 30 to 200 MHz. Its cycle-to-cycle rms jitter is 12.8 ps at 133 MHz, and it dissipates 30 mW at 2.5 V.

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-/spl mu/m CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm/sup 2/) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7].