Wide Lock Research Articles

Educational Stress of Student during Lockdown Period that Inturn Shapes Their Career

The entire world is going through a crisis on account of the Global Pandemic. After the surge in the cases in the early March 2020, the policy makers, the doctors, and the experts in the field of Virus Epidemiology took a call of nation -wide lock down. Since, there is no immediate cure available, physical distancing is seen as the only solution to curb the spread that could create a panic. The nationwide lockdown has consequences on various spheres of public life, government, and informal sectors and also on the education sector. The lockdown has resulted in schools, college universities being shut for more than a month now. The academic session in the schools was about to end and examinations had started in some schools and some were in the middle of the examination process. Universities work in full swing during this time of the year as it is the time for semester assessments and completion of the syllabus is on wheels. Educational institutes across the length and breadth of the country are temporarily closed to contain the spread of Corona infection. The decision of the Government needs to be appreciated as the schools and other educational institutes cater to the younger, dynamic, and most productive chunk of our population and it is the duty of the Government to protect the youth and hence the closure was inevitable. It is also becoming increasingly clear that the present lockdown is not going to end soon as the infection rate is escalating in almost all states.

Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

ABSTRACTThis article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low.

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fs rms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB.

An Implementation of Wide-Range Digital Delay Locked Loop

This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-/spl mu/m CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370/spl times/510 /spl mu/m/sup 2/, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively.