Wideband Voltage-controlled Oscillator Research Articles

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a Gm−C filter is proposed. The reference spur is improved by 7 dB when compared with one without any Gm−C filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The Gm−C filter block consumes 200 μA current. The wideband voltage-controlled oscillator (VCO) oscillates from 1.6 GHz to 3.2 GHz having a tuning range (TR) of 40%, achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈−116 dBc/Hz at a 1 MHz offset, respectively.

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

An Ultra-Low-Power Octave-Tuning VCO IC With a Single Analog Voltage-Controlled Novel Varactor

In this paper, an ultra-low-power octave-tuning voltage-controlled oscillator (VCO) integrated circuit (IC) is proposed, using a novel varactor with a single control voltage. The novel varactor including VCO-gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K} _{\mathrm{ VCO}}$ </tex-math></inline-formula> ) improving structure consists of two parallel-connected inversion-mode MOS (I-MOS) -based varactors with shifted bias and an NMOSFET operating as a variable resistor. This novel varactor is able to give a large capacitance variation with a single analog control voltage. The proposed wideband VCO IC implementing this novel varactor is designed, fabricated, and evaluated fully on-wafer in 40-nm CMOS SOI technology. The proposed wideband VCO IC has exhibited a completely continuous measured tuning range (TR) of 67.9% from 3.2 to 6.49 GHz. The measured dc power consumption is from 0.35 to 1.36 mW throughout the whole TR under a supply voltage of 0.36 V. This is an extremely low dc power consumption among the reported sub-10-GHz octave-tuning VCO ICs so far. The measured peak figure-of-merit including TR (FoMT) of the proposed VCO IC is 210.4 dBc/Hz with a carrier frequency of 6.49 GHz.

A 0.023–12 GHz ultra-wideband frequency synthesizer with FOMT of −251.8 dB

A fully integrated ultra-wideband fractional-N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional-N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional-N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOMT of −251.8 dB.

X-band CMOS VCO for 5 GHz Wireless LAN

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of –122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

4.02-5.48 GHz wideband VCO with coupling reduction and small Kvco variation

ABSTRACT A wideband voltage-controlled oscillator (VCO) with coupling reduction and small VCO gain () variation has been fabricated for multi-standard RF transceivers. A high-quality factor 8-shaped inductor is adopted to reduce the magnetic coupling between inductors and optimise the phase noise of the VCO. Electromagnetic simulations of magnetic coupling are carried out between an octagonal inductor and an 8-shaped inductor, and as high as 36 dB reduction in magnetic coupling is achieved by using 8-shaped inductors. A novel varactor group is proposed to realise a constant in the fine-tuning process, in which the scheme adopts an inversion-mode MOS varactor to revise the capacitance variation of an accumulation-mode MOS varactor. Meanwhile, an extra 3-bit varactor array is employed to reduce variation in the coarse tuning process. Based on a conventional TSMC 0.18-μm CMOS process, a nearly constant of 58 MHz/V is obtained for a wide frequency range of 4.02 to 5.48 GHz. The proposed VCO achieves a phase noise of less than −119.8 dBc/Hz at 1 MHz offset. The current consumption is 4.3–8.8 mA under a source voltage of 1.8 V.

A Synthesizable Constant Tuning Gain Technique for Wideband $LC$ -VCO Design

In this paper, an iterative method is proposed for the optimization of wideband voltage-controlled oscillators (VCOs). The proposed method attempts to improve two significant performance metrics of wideband VCOs, i.e., the nonuniform band distribution and the nonconstant tuning gain ${K} _{\text{VCO}}$ . To address these nonideality issues, we introduce the deviation as a prior knowledge for calibration in each iteration step. The optimal capacitor array weighting plan can be asymptotically approached through multiple iterations. To demonstrate the efficacy of the proposed method, we use it to implement a 1-to-2.4-GHz LC -VCO and achieve a frequency tuning range of 82.4%. The optimized LC -tank involves 64 mixed cells, and each cell contains 2-bit binary-weighted switching capacitors, leading to 256 tuning bands. The LC -VCO with the synthesized tank achieves uniform frequency steps around 5 MHz with the relative error within ±4.4%. Meanwhile, the tuning gain ${K} _{\text{VCO}}$ is around 10 MHz/V with the relative error within ±3.2%. For this LC -VCO design, each iteration step costs about 55.9 s. After seven iterations, we approach the convergent solution where both the relative errors of the frequency steps and the tuning gains satisfy the given specifications.

Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.

A 2-15 GHz VCO With Harmonic Cancellation for Wide-Band Systems

A 2-15 GHz SiGe VCO (voltage controlled oscillator) has been developed with a very low harmonic content. The design is based on the harmonic cancellation concept and uses a multiple-phase ring oscillator together with a wide-band active-weighted summer. The VCO results in an output power of −8 to −6 dBm and $3^{rd}$ and $5^{th}$ harmonic level at 2-15 GHz. The active area of the chip is very small ( $0.67 \times 0.25$ mm2) due to the lack of inductors, and the power consumption is 88-120 mW from a 2.5 V supply. To our knowledge, this is the first demonstration of a wide-band VCO showing a near-perfect sinewave output over a wide frequency range. The application areas are in built-in-self-test sources for wide-band radios and phased arrays.

Analysis and Design of Wide-Band Millimeter-Wave Transformer-Based VCO and ILFDs

Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of -112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of -180.4 dBc/Hz and -187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW.

SAW-LC coupled resonator wideband VCO for medical telemetry.

Wireless links with implantable devices can help in real-time monitoring of symptoms, irregularities, implanted device efficacy and their reconfiguration. We present the design of a low-power wideband voltage controlled oscillator (VCO) to facilitate implantable wireless telemetry. A coupled SAW-LC resonator design combines high Q and spectral purity of a SAW element and tunability of an LC-tank. The designed 2.7 MHz bandwidth VCO is suitable for full duplex communication protocols in the MedRadio band with frequency agility and higher duty cycles, in conformance with FCC regulations. Output power at the fundamental frequency is above -7.5 dBm for a wide range of load impedances. Output power load insensitivity provides a wide margin for selection of communication system parameters, variability in device placement, temporal variation in tissue properties and flexibility for implants at different locations (e.g. heart, gastrointestinal tract, brain). The maximum output power variation in the entire 2.7 MHz band is limited to 1.3 dBm. Sensitivity of oscillation frequency to loading can be addressed by individual device calibration. The small size, component count and low DC power consumption (1.9 V, ~1.95 mW) is favorable for including in a miniaturized and integrated design assembly with a battery-powered implanted device.

A SiGe Fractional-${ N}$ Frequency Synthesizer for mm-Wave Wideband FMCW Radar Transceivers

A millimeter-wave (mm-wave) frequency synthesizer is presented focusing on an ultra-high-speed fractional- ${ N}$ frequency divider and a highly linear phase-frequency detector (PFD). All circuits are integrated into a high-frequency SiGe bipolar technology. The programmable frequency divider can be operated at input frequencies between dc and 57 GHz for division factors in the entire integer range from 12 to 259. The PFD is optimized for fractional- ${ N}$ synthesis, which requires an extremely linear characteristic due to the modulation of its input frequency. The frequency divider and the PFD are used together with an 80-GHz wideband voltage-controlled oscillator (VCO) and transceiver for a high precision mm-wave frequency-modulated continuous-wave (FMCW) radar sensor. As shown by the experimental results the realized circuits stabilize the mm-wave VCO with an extremely low phase noise below $-{\hbox{97 dBc/Hz}}$ at 10-kHz offset around its center frequency of 80 GHz and can generate a highly linear frequency ramp with a bandwidth of 24 GHz. Furthermore, the accuracy of the synthesizer is demonstrated by FMCW radar distance measurements inside a waveguide and in free space. Inside the waveguide a standard deviation of the phase of the target below 0.0018 $^{\circ }$ (which corresponds to 9.4 nm) was measured.

Low‐phase‐noise wideband VCO with optimised sub‐nH inductor

A wideband voltage-controlled oscillator (VCO) covering 2.24–4.95 GHz for multi-standard wireless applications is presented. Realised in TSMC 180 nm RFCMOS process, the VCO provides a phase noise <–124.2 dBc/Hz at a 1 MHz offset in the whole frequency range, while drawing 10 and 18 mA at 4.95and 2.24 GHz from a 1.8 V supply, respectively. The achieved tuning range is 75% and the core chip area is 0.51 mm².

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an in-phase/quadrature-phase (I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation (WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator (VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 kHz loop bandwidth, lowest measured phase noise is −106 dBc/Hz at a 10 kHz offset and −131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 mW from the 1.8 V power supply, and settles within 13.2 μs. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.

Ultra-Wideband VCO Phase-Noise Reduction Loop Based on a Six-Port Phase-Shifterless Delay-Line Discriminator

In this paper, a novel frequency-locked loop (FLL) architecture for phase-noise reduction of wideband voltage-controlled oscillators (VCO) is presented. The circuit makes use of a phase-shifterless frequency discriminator, which completely avoids the use of any control circuitry to keep the loop in its quadrature condition, highly simplifying the loop. The FLL circuit, which can be operated in a completely transparent way, can be easily interchangeable with the original VCO. An FLL prototype, based on a commercial state-of-the-art VCO, has been fabricated and measured exhibiting a phase-noise reduction higher than 9 and 5.5 dB up to 100-kHz and 1-MHz offset from carrier, respectively, in the complete 4.6-9-GHz band. Absolute phase noise results of -106.5 and -124 dBc/Hz at 100-kHz and 1-MHz offset from carrier have been obtained, showing lower phase noise than other wideband FLLs in the literature.

A Wideband Voltage-Controlled Oscillator With Gain Linearized Varactor Bank

A new gain linearized varactor bank suitable for wideband voltage-controlled oscillators (VCOs) is presented in this paper. The VCO tuning gain linearized techniques, namely the gain variation compensation and linear tuning range extension techniques, are used in the proposed varactor bank to achieve a further reduced VCO tuning gain with low variation. The phase noise from Amplitude Modulation to Phase Modulation up conversion is considerably improved thanks to the reduced VCO tuning gain. Fabricated in a 0.18-μm CMOS technology, a 3-bits VCO prototype employing the proposed varactor bank achieves <;5% gain variation at the output frequency from 4.1 to 5 GHz, and exhibits maximum power consumption of 7.2 mW at its peak frequency, 5 GHz.

A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars

This paper describes a frequency synthesizer for frequency-modulated continuous wave (FMCW) radars, operating in combination with a frequency multiplier, at 77 GHz. The fractional-N phase-locked loop (PLL)-based synthesizer is equipped with a wideband voltage-controlled oscillator, which is realized with CMOS transistors in a current-reuse technique, and a delay-locked loop (DLL). Utilized as a frequency multiplier for the reference signal, the DLL improves both the phase noise performance of the PLL and the linearity of the frequency sweep generated by the PLL. Two types of voltage-controlled delay lines used in the DLL are also introduced and compared in this paper. Both show a good performance in terms of phase noise and can be easily realized in a standard CMOS technology. The false-lock issue of the DLL is also discussed and a solution is proposed. Furthermore, a frequency multiplier is used to multiply the output frequency of the PLL by a multiplication factor of 18. This architecture enables an increase in the target resolution and an improvement in the accuracy of the measurements of FMCW radars.

Design of Low Phase-Noise Oscillators and Wideband VCOs in InGaP HBT Technology

A method for design of low phase-noise balanced-Colpitts (BC) fixed-frequency oscillators (FFOs) and wideband voltage-controlled oscillators (VCOs) is presented. Analytical expressions describe how to design an oscillator for best phase noise, given a limited Q factor and a certain active device. The theory needs only two free parameters: the impedance level (Zc) and tapping ratio (n) of the resonator. It is described how to chose ZC and n for low phase noise and large tuning range, respectively. The design method is verified with a low phase-noise FFO and a wideband VCO, both designed in InGaP HBT technology. The BC FFO presents a phase noise of 112 dBc/Hz at 100-kHz offset from a 9.2-GHz carrier. The wideband VCO implemented in the same technology presents a minimum phase noise of 106 dBc/Hz at 100-kHz offset from a 9-GHz carrier. Over the frequency range of 8.4-9.7 GHz, the phase noise is better than 102 dBc/Hz and the output power is 7 0.5 dBm. The wide tuning range, constant output power, and relatively constant and low phase noise are achieved due to double pairs of tuning varactors, one between emitters and one between collectors. To the authors' best knowledge, this type of double-tuned BC VCO topology has not been previously published.

A 10 GHz wideband VCO with low KVCO variation

This paper presents a novel topology for a 10GHz voltage controlled oscillator (VCO). The design uses a differential delay cell architecture with four stages. It achieves a wide frequency range of (2–10) GHz and a maximum KVCO variation of 2.5 by using a voltage controlled resistor (VCR) that has a programmable size to reduce the impact of temperature and process corners variations. The design uses a 1V supply and consumes a maximum power of 18mW. It was extracted and simulated in 90nm CMOS technology.

Design of Low Phase-Noise Microwave Oscillator and Wideband VCO Based on Microstrip Combline Bandpass Filters

This paper presents a new low phase-noise microwave oscillator and wideband voltage-controlled oscillator (VCO) based on microstrip combline bandpass filters. For this type of oscillator, the passband filter is embedded into the feedback loop to treat as a frequency stabilization element. Instead of designing the oscillator at the group-delay-peak frequency of the filter to achieve a good phase-noise performance, in this paper, the peak frequency of the complex quality factor Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> is adopted for oscillator design. To demonstrate the effectiveness of using Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> -peak frequency, two filter-based oscillators are implemented at the Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> -peak and group-delay-peak frequencies, respectively. The oscillator designed at the Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sc</sub> -peak frequency improves the phase-noise about 10 dB as compared with that realized at the group-delay-peak frequency. The developed oscillator with the three-pole combline filter is experimentally demonstrated at 2.05 GHz with -148.3-dBc/Hz phase noise at 1-MHz offset frequency. Moreover, by attaching a varactor on each resonator of the combline filter, the oscillator can be extended to a wideband VCO. The developed VCO has a frequency tuning range from 1.3 to 2.2813 GHz with a 54.8% bandwidth. Over this frequency range, all the phase noises measured at 1-MHz offset frequency are better than -117.19 dBc/Hz.