Wafer Quality Control Research Articles

Three-Dimensional Profile Reconstruction and Internal Defect Detection of Silicon Wafers Using Cascaded Fiber Optic Fabry–Pérot Interferometer and Leaky Field Detection Technologies

Abstract Wafer quality control is one of the important processes to improve the yield rate of semiconductor products. Profile quality and defects in the wafer are two key factors that should be taken into consideration. In this research, we introduce a method that measures the profile of the upper surface and the thickness of the wafer at the same time using an optical fiber cascaded Fabry–Pérot interferometer working at wavelength of 1550 nm. Therefore, the 3D profile of the wafer can be reconstructed directly. Testing results show that both accuracy and precision of the Fabry–Pérot interferometer are within a nanometer scale. Defects, especially those embedded inside the wafer, will be detected by monitoring the leaky field with treating wafers as slab waveguides. With the leaky field detection, defects on the lower surface of the wafer were successfully detected by monitoring the leaky field above the upper surface of the wafer. Compared with traditional methods such as radiographic testing or computed tomography testing, the proposed methods provide a cost-effective alternative for wafer quality evaluation.

Application of light scattering tomography for Si(111) samples.

The detection of bulk micro-defects in Czochralski-grown silicon (Si) 〈100〉 wafers has significant importance in wafer quality control. Light Scattering Tomography (LST) is an industry standard technique for this purpose. This optical non-contact metrology requires destructive sample preparation: Samples have to be cleaved into half. One particular feature of the method is a dark field detection arrangement, which is achieved by separating the light detection part (microscope unit) from the illumination. Illumination is applied to the front surface of the sample, and the light scattered off of the defects is collected via the cleaved surface. The technique requires the perpendicularity of the cleaved surface to the front surface, which is fulfilled for Si(100) wafers. However, the nominally cleaved surface for Si(111) wafers is not perpendicular to the front surface but has an angle of 70.5°. This significant difference in cleavage results in the fact that Si(111) wafers cannot be measured by standard LST systems. Fortunately, the standard LST system can be modified by tilting the detection part under a proper angle allowing the measurements of Si(111) samples. In this article, we present this new technique in detail, showing the design and measurement capability of the new system. The measurement results are validated by a direct comparison to standard LST measurements on the same samples after proper sample preparation.

Wafer Delay Analysis and Workload Balancing of Parallel Chambers for Dual-Armed Cluster Tools With Multiple Wafer Types

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time. Note to Practitioners —Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

Multi-step virtual metrology for semiconductor manufacturing: A multilevel and regularization methods-based approach

In semiconductor manufacturing, wafer quality control strongly relies on product monitoring and physical metrology. However, the involved metrology operations, generally performed by means of scanning electron microscopes, are particularly cost-intensive and time-consuming. For this reason, in common practice a small subset only of a productive lot is measured at the metrology stations and it is devoted to represent the entire lot. Virtual Metrology (VM) methodologies are used to obtain reliable predictions of metrology results at process time, without actually performing physical measurements. This goal is usually achieved by means of statistical models and by linking process data and context information to target measurements. Since semiconductor manufacturing processes involve a high number of sequential operations, it is reasonable to assume that the quality features of a given wafer (such as layer thickness and critical dimensions) depend on the whole processing and not on the last step before measurement only. In this paper, we investigate the possibilities to enhance VM prediction accuracy by exploiting the knowledge collected in the previous process steps. We present two different schemes of multi-step VM, along with dataset preparation indications. Special emphasis is placed on regression techniques capable of handling high-dimensional input spaces. The proposed multi-step approaches are tested on industrial production data.

A Unified Framework for Outlier Detection in Trace Data Analysis

Process trace data (PTD) is an important data type in semiconductor manufacturing and has a very large aggregate volume. While data mining and statistical analysis play a key role in the quality control of wafers, the existence of outliers adversely affects the applications benefiting from PTD analysis. Due to the complexities of PTD and the resultant outlier patterns, this paper proposes a unified outlier detection framework which takes advantages of data complexity reduction using entropy and abrupt change detection using cumulative sum (CUSUM) method. To meet the practical needs of PTD analysis, a two-step algorithm taking into account of the related domain knowledge is developed, and its effectiveness is validated by using real PTD sets and a production example. The experimental results show that the proposed method outperforms the Fast Greedy Algorithm (FGA) and the Grubb's test, two commonly used outlier detection techniques for univariate data.

Contactless resistivity mapping of semi-insulating substrates

High susbtrate resistivity is an important competitive asset of III–V semiconductors. It enhances the performance of ultrafast microelectronic and optoelectronic circuits. For a thorough on-line wafer quality control, a superior measurement system is required to evaluate resistivity fast, nondestructively and with high lateral resolution.

Vacancy concentration wafer mapping in silicon

A method is described, which for the first time allows the fast determination of the concentration of vacancies and the visualization of their inhomogeneity in silicon wafers. The vacancy concentration wafer mapping is suggested as a means for the determination of the quality of silicon wafers. The concentration of vacancies is determined via the measurement of the concentration of fast diffusing elements, especially platinum or gold, which occupy silicon vacancies. Platinum and gold introduce deep energy levels in the bandgap, which act as recombination centers for excess carriers, whether excess electrons or holes, and the platinum or gold concentration can be obtained from excess carrier lifetime measurements. Several important applications of this method are suggested such as the optimization of the crystal growth manufacturing process, wafer quality control, and the selection of wafers for the fabrication of specific devices.

End station design and wafer quality control for a high current oxygen implanter

The end station of the Eaton NV-200 high current oxygen implanter is described. In this machine the beam enters at 30° from the horizontal and the wafers are mounted on the inside surface of a slightly conical drum which rotates about a vertical axis. A cone half angle of 16° results in an implant angle of 14°. The drum rotates at a high speed and the beam is broadened into a line which fully illuminates the wafers without scanning, resulting in a uniform implant as the wafers pass through it on the rotating drum. By adjusting the ion source apertures and beam line optics implant uniformity within a few percent has been achieved over the whole wafer. The drum holds twenty-five 4 in. wafers per batch. Sampling holes located in the drum together with a Faraday plate in the end station are used to monitor beam uniformity. Dose measurement is done calorimetrically using the power into the end station to calculate the integrated dose. The end station is equipped with heater lamps which will preheat the wafers to the desired temperature before the implantation process is begun. These lamps are also utilized to maintain the wafers at an elevated temperature if the implant is interrupted.

Lang camera for large scale X-ray transmission topography. (Nondestructive test method for Si wafer quality control)

An X-ray topography camera of the Lang type with a scanning range of about 30 cm is described which is capable of recording in one run topographs of e.g. four 3 in diameter silicon wafers. Camera performance and the use of the setup for quality control of large diameter silicon wafers are illustrated.