Wafer Map Defect Research Articles

DMWMNet: A novel dual-branch multi-level convolutional network for high-performance mixed-type wafer map defect detection in semiconductor manufacturing

Wafer map defect detection plays an important role in semiconductor manufacturing by identifying root causes and accelerating process adjustments to ensure product quality and reduce unnecessary expenditures. However, existing methods have some limitations, such as low accuracy in mixed-type defect detection and poor recognition of similar defects and weak features. In this article, a novel dual-branch multi-level convolutional network (DMWMNet) is proposed for high-performance mixed-type wafer map defect detection. By fully considering the interrelationships between basic defects, defect number, and defect type, the network is designed to include two efficient parallel Branches and a Fusion classifier. Detecting defect types using basic defect discrimination and defect number detection is helpful for ameliorating problems with high complexity and low accuracy caused by multiple defect categories and feature overlaps. Furthermore, a composite loss function based on focal loss is employed to improve the network’s capacity to recognize weak features and similar defects. Experimental results on the MixedWM38 dataset show that DMWMNet has favorable mixed-type defect detection performance compared to other methods, with accuracy, precision, recall, F1 score, and MCC of 98.99%, 98.94%, 99.03%, 98.98%, and 98.97%, respectively.

Improved wafer map defect pattern classification using automatic data augmentation based lightweight encoder network in contrastive learning

Improved wafer map defect pattern classification using automatic data augmentation based lightweight encoder network in contrastive learning

A new ViT-Based augmentation framework for wafer map defect classification to enhance the resilience of semiconductor supply chains

Wafer map defect classification plays a crucial role in sustaining the semiconductor supply chain during industrial disruptions by ensuring continuity, resilience, and efficiency while aligning with sustainability principles. Up to 30 percent of production costs is lost to chip testing and yield losses for semiconductor manufacturing supply chain. In the semiconductor practice, wafer map defects recognition plays a linchpin role in the front-end-of-line stage. Defect pattern recognition can directly pinpoint the assignable causes and provide the domain experts with actionable insights. However, various wafer defect types occur differently from each other, which makes the collected wafer map dataset to be highly imbalanced in defect classes. In the face of data imbalance, the classification model usually cannot provide satisfactory classification performance. In this aspect, this paper intends to investigate the wafer defect map classification problem by using Vision Transformer (ViT) as an alternative data augmentation approach. The primary purpose is to alleviate the class-imbalance issue and then the performance of a deep learning-based convolutional neural network for wafer defect classification can be effectively improved. The experimental results demonstrate that the proposed data augmentation method by using ViT proves to be a potential generative model for improving wafer map defect classification, particularly robust on the individual minority class. In a word, the proposed augmentation framework for wafer map defect classification facilitates a more targeted and efficient approach to quality control, resource utilization, and production optimization in maintaining a sustainable semiconductor supply chain, particularly in times of industrial disruption.

Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition

In wafer map defect pattern recognition, deep learning methods are predominantly used. These models autonomously learn features without explicit human intervention due to their black-box type network architectures. While preceding feature extraction and modality representation may seem neglected in deep learning for wafer map defect pattern recognition, we addressed this question by proposing an innovative approach. Our proposed method employs an antecedent feature learning module to create a more compact and informative hash modality representation from input wafer maps. The method exceeds in achieving high recall, crucial for identifying actual defective wafers as much as possible in semiconductor manufacturing, where defects can impact integrated circuit functionality and reliability. Smaller-sized hash modalities against larger wafer maps allow the same model to speed up the process and require fewer computational resources.

Classification of wafer map defect based on ResNeSt

With the increasing circuit complexity of chip design, wafers are prone to defects in the production process. Since different defects have their causes, post-analysis is important to wafer production. However, the sample size is not balanced, and the effect of classical residual networks is limited. This article uses a Split-Attention network (ResNeSt) with which feature maps will be input into k-base groups, each consisting of r groups. Thanks to the large receptive field, image features can be obtained better. We add channel attention and give higher weight to the effective feature channels to improve network performance. Compared with the classical residual network, the new network has an improvement of 43.06%, 32.73%, and 10.86% in handling Scratch, Near-full, and Local defects, respectively.

An efficient deep learning framework for mixed-type wafer map defect pattern recognition

Defect detection on wafers holds immense significance in producing micro- and nano-semiconductors. As manufacturing processes grow in complexity, wafer maps may display a mixture of defect types, necessitating the utilization of more intricate deep learning models for effective feature learning. However, sophisticated models come with a demand for substantial computational resources. In this paper, we propose an efficient deep learning framework designed explicitly for mix-type wafer map defect pattern recognition. Our proposed model incorporates several crucial design elements, including lightweight convolutions, bottleneck residual connections, efficient channel attention mechanisms, and optimized activation functions, enabling it to learn spatial and channel features efficiently. We conduct evaluations on a real-world dataset containing 38 mixed-type defect patterns. The experimental results demonstrate that our framework maintains a high level of accuracy while possessing a compact parameter size and remarkably fast inference speed.

Unsupervised Representation Learning for Large-Scale Wafer Maps in Micro-Electronic Manufacturing

Recognition of wafer map defect patterns is essential for evaluating the reliability of micro-electronic manufacturing. Due to the difficulty of labeling, the available large-scale wafer maps are raw data without labeling. The scarcity of labeled samples reduces the defect pattern recognition accuracy of popular deep convolutional neural networks. To overcome this problem, we propose a wafer map deep clustering (WMDC) model. It learns generic representations from unlabeled datasets in an unsupervised manner. A prototype metric loss during training helps to learn the semantic features of the categories. We improve the recognition accuracy of the model when trained using scarce labeled data by transferring the weights of unsupervised pretraining. Experiments on WM811K and MixedWM38 wafer datasets demonstrate that the WMDC model is capable of obtaining robust prior representations from the unlabeled wafer maps. Accuracies of 97.43% and 98.74% are obtained when fine-tuning using scarce labeled data from both datasets, respectively.

Large-Margin Extreme Learning Machines With Hybrid Features for Wafer Map Defect Recognition

Large-Margin Extreme Learning Machines With Hybrid Features for Wafer Map Defect Recognition

Wafer map defect recognition based on multi-scale feature fusion and attention spatial pyramid pooling

Wafer map defect recognition based on multi-scale feature fusion and attention spatial pyramid pooling

Wafer map defect pattern detection method based on improved attention mechanism

Wafer map defect pattern recognition is an indispensable part in the semiconductor manufacturing process. Wafer map defect pattern recognition and classification can locate the cause of failures in the manufacturing process. In this study, we propose a deep convolutional neural network architecture incorporating improved convolutional block attention module (I-CBAM) for pattern recognition and classification of single-type wafer map defects. The proposed method consists of three steps: First, a multi-branch attention module is designed, which focuses more on the main information of defect clusters, extracts richer feature information, and improves feature extraction capabilities. Secondly, I-CBAM is integrated into the ResneXt50 backbone network to extract wafer map defect features. Finally, the extracted features are fed to a support vector machine combined with an error-correcting output code to classify the wafer map defect pattern. The experimental results on the real-world datasets WM-811K show that the accuracy rate of the I-CBAM-ResneXt50 can reach 96.96%. Compared with the existing algorithms, the proposed model can achieve better recognition and classification results.

Wafer map failure pattern classification using geometric transformation-invariant convolutional neural network

Wafer map defect pattern classification is essential in semiconductor manufacturing processes for increasing production yield and quality by providing key root-cause information. However, manual diagnosis by field experts is difficult in large-scale production situations, and existing deep-learning frameworks require a large quantity of data for learning. To address this, we propose a novel rotation- and flip-invariant method based on the labeling rule that the wafer map defect pattern has no effect on the rotation and flip of labels, achieving class discriminant performance in scarce data situations. The method utilizes a convolutional neural network (CNN) backbone with a Radon transformation and kernel flip to achieve geometrical invariance. The Radon feature serves as a rotation-equivariant bridge for translation-invariant CNNs, while the kernel flip module enables the model to be flip-invariant. We validated our method through extensive qualitative and quantitative experiments. For qualitative analysis, we suggest a multi-branch layer-wise relevance propagation to properly explain the model decision. For quantitative analysis, the superiority of the proposed method was validated with an ablation study. In addition, we verified the generalization performance of the proposed method to rotation and flip invariants for out-of-distribution data using rotation and flip augmented test sets.

Evolutionary computation-based reliability quantification and its application in big data analysis on semiconductor manufacturing

Big data analysis of wafer maps in semiconductor manufacturing is essential for process reliability assessment, it is an important means of fault diagnosis in manufacturing. Although many excellent wafer map defect pattern identification (WMDPI) methods have been proposed, such as deep convolutional neural network (DCNN) based methods, there is no method that can make completely correct decisions and avoid false detections. Decision reliability is critical to the training evolution process of DCNN. In this paper, we propose a reliability quantification algorithm for wafer big data analysis. We estimate the parameter evolution uncertainty of DCNN in the WMDPI process by mixed uncertainty and thus quantify the decision reliability. In particular, reliability assessment is achieved by quantifying hybrid uncertainties, including epistemic uncertainty and aleatoric uncertainty. For epistemic uncertainty, this paper uses Monte Carlo dropout and explores the effects of drop rate, action location, and uncertainty criteria on reliability quantification through an empirical study. For aleatoric uncertainty, this paper proposes a calculation method based on Monte Carlo augmentation. The experimental results show that the identification accuracy of unknown defect patterns is 97.04% when hybrid uncertainty is considered; the identification accuracy of known defect patterns can be improved by up to 7.89%. The proposed DCNN can effectively avoid false and missed detections in the process of wafer big data analysis.

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.

Wafer Map Defect Pattern Detection Method Based on Improved Attention Mechanism

Wafer Map Defect Pattern Detection Method Based on Improved Attention Mechanism

A systemic comparison between using augmented data and synthetic data as means of enhancing wafermap defect classification

The analysis of defects in wafermaps is a very crucial task in enhancing the yield. With a fast defect classification, companies can address the root cause of the problem and thus increase the yield quickly. Several researchers have used the WM-811K dataset to train and test their machine learning models, but with only 3.1% of the wafers labeled in this dataset. Researchers resorted to using supplementary techniques, such as augmented data and synthetic data to train the model.This paper standardized the comparison between the use of augmented data and synthetic data to enhance the WM-811K dataset. This standardization process is achieved by attempting to balance the dataset used across different defect classes. In addition, defining per-class performance metrics that are not swayed by any data imbalance. Using support vector machine classifier, the results show that synthetic data is superior to augmented data as it performed better in terms of accuracy (82.7% Vs. 78.5%), recall (83.7% Vs. 79.5%), precision (84.4% Vs. 79.9%), and F1-score (84.1% Vs. 79.7%). These results were consistent using other classifiers like linear regression, random forest, and artificial neural networks. The paper also shows that the enhanced performance achieved using the synthetic data is more uniform across all the defect classes.

High Accuracy Swin Transformers for Imagebased Wafer Map Defect Detection

High Accuracy Swin Transformers for Imagebased Wafer Map Defect Detection

Advances in machine learning and deep learning applications towards wafer map defect recognition and classification: a review

Advances in machine learning and deep learning applications towards wafer map defect recognition and classification: a review

Wafer map defect patterns classification based on a lightweight network and data augmentation

AbstractAccurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines. During the wafer testing stage, deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capabilities. However, most of the current wafer defect patterns classification models have high complexity and slow detection speed, which are difficult to apply in the actual wafer production process. In addition, there is a data imbalance in the wafer dataset that seriously affects the training results of the model. To reduce the complexity of the deep model without affecting the wafer feature expression, this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module. In addition, to reduce the impact of data imbalance on model training, this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer. The method proposed in this paper has an average accuracy of 95.4% on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs, and takes only 22.99 s to detect 1000 wafer pictures. Compared with the original PeleeNet network without optimization, the number of parameters and FLOPs are reduced by 92.68% and 58.85%, respectively. Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8% on the WM‐811K dataset. At the same time, the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.

Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning

Wafer map defect patterns provide valuable information for root cause analysis and yield learning. Previous studies show that supervised machine learning (ML) methods can achieve good defect pattern recognition rate. However, the effectiveness of these methods rely on accurately labeled samples, which leads to two problems. First, oftentimes there are mislabeled data, which may prevent an accurate model from being established. Secondly, defect patterns that are not defined a priori will not be recognized. In this paper, we propose a semi-supervised learning method to deal with these problems. Labeled wafer maps are first used to train a prediction model, and questionable samples are excluded in the process. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns for enhanced labeling. The proposed approach is validated using the WM-811K database. With the proposed method, we are able to define five new defect pattern types, and the 14 defect types can be recognized with high accuracy.

WDP-BNN: Efficient wafer defect pattern classification via binarized neural network

Wafer map defect pattern classification using convolutional neural network (CNN) has gained a lot of attention in recent years but it demands huge computation and memory cost. Therefore, a WDP-BNN framework based on the binarized neural network is proposed to reduce memory requirement by 29.70× and speed up by 1.66×. To overcome the imbalance problem and performance loss due to binarization of network, advanced data augmentation methods including (Chip Reverse, Chip Translate, Chip Combine) along with random under-sampling method have incorporated in the framework. Experimental results on the WM-811K dataset have demonstrated that the WDP-BNN model has outperformed the state-of-the-art works with the highest classification accuracy of 94.83% and the memory reduction of 1.10-25.93×.