Wafer-level Vacuum Packaging Technology Research Articles

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances

We present the novel 3D wafer-level vacuum packaging technology for MEMS, which only needs two masks and is realized by Au-Si eutectic bonding with a low-resistivity Si Cap wafer. Wherein, Au-Si bonding pads and rings are formed to accomplish vertical interconnects and a vacuum package respectively. Applied to resonators with two typical substrate wafers of Si and Glass, this 3D package structure has further gone through the systemic characterizations. Specifically, the high-reliable mechanic strengths of device packages are revealed from Au-Si bonding strengths measured as about 20 MPa in tensile tests. Based on analyzing parasitic capacitance networks in device packages, the feed-through effect in resonance tests can be effectively relieved by grounding on each Si layer in device package structures (i.e. the parasitic capacitance reduced from the level of pF to fF). By resonance tests, it is found that increasing the degassing duration (30 min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 60$ </tex-math></inline-formula> min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> min) is beneficial for improving package vacuum degrees as well as consistencies (69% within 4–30 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 88$ </tex-math></inline-formula> % within 0.6-1.2 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 85$ </tex-math></inline-formula> % within 0.6-0.8 kPa), and hermetic package yields (73% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 86$ </tex-math></inline-formula> % <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> %). Besides, device packages are verified to have good long-term stability by monitoring quality factor variations in 6 months. Overall, this proposed 3D packaging technology has extensive application prospects in various MEMS devices due to its inherently-simple process, low capacitive feed-through effect, and fine package performances. Also, test results provide instructions on the realization of low-parasitic-capacitance signal interfaces and the optimization of wafer-level vacuum package processes.

The Design and Simulation of Vibratory Ring Gyroscope

This paper deals with design and simulation of vibratory ring gyroscope which has good performance as resisting vibration, resisting impact, small temperature drift because of the inherent symmetry of structure. The good performance of gyroscope has verified by detailed modeling and simulation. The manufacture of gyroscope using wafer level vacuum packaging technology making the gyroscope has high quality factor .At last we test the gyroscope and the Q factor is 20300 by detecting the resonant state of the gyroscope.

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

Imaging in the long wavelength infrared (LWIR) range from 8 to 14μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25μm×25μm that are arranged on read-out-wafers in arrays with 320×240pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of −3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu–Sn solid–liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Design and fabrication of high performance wafer-level vacuum packaging based on glass–silicon–glass bonding techniques

In this paper, a high performance wafer-level vacuum packaging technology based on GSG triple-layer sealing structure for encapsulating large mass inertial MEMS devices fabricated by silicon-on-glass bulk micromachining technology is presented. Roughness controlling strategy of bonding surfaces was proposed and described in detail. Silicon substrate was thinned and polished by CMP after the first bonding with the glass substrate and was then bonded with the glass micro-cap. Zr thin film was embedded into the concave of the micro-cap by a shadow-mask technique. The glass substrate was thinned to about 100 µm, wet etched through and metalized for realizing vertical feedthrough. During the fabrication, all patterning processes were operated carefully so as to reduce extrusive fragments to as little as possible. In addition, a high-performance micro-Pirani vacuum gauge was integrated into the package for monitoring the pressure and the leak rate further. The result shows that the pressure in the package is about 120 Pa and has no obvious change for more than one year indicating 10−13 stdcc s−1 leak rate.

High-Q MEMS Resonators for Laser Beam Scanning Displays

This paper reports on design, fabrication and characterization of high-Q MEMS resonators to be used in optical applications like laser displays and LIDAR range sensors. Stacked vertical comb drives for electrostatic actuation of single-axis scanners and biaxial MEMS mirrors were realized in a dual layer polysilicon SOI process. High Q-factors up to 145,000 have been achieved applying wafer level vacuum packaging technology including deposition of titanium thin film getters. The effective reduction of gas damping allows the MEMS actuator to achieve large amplitudes at high oscillation frequencies while driving voltage and power consumption can be minimized. Exemplarily shown is a micro scanner that achieves a total optical scan angle of 86 degrees at a resonant frequency of 30.8 kHz, which fulfills the requirements for HD720 resolution. Furthermore, results of a new wafer based glass-forming technology for fabrication of three dimensionally shaped glass lids with tilted optical windows are presented.