Wafer-level Vacuum Packaging Research Articles

Wafer Level Vacuum Packaging of MEMS-Based Uncooled Infrared Sensors.

This paper introduces a cost-effective, high-performance approach to achieving wafer level vacuum packaging (WLVP) for MEMS-based uncooled infrared sensors. Reliable and hermetic packages for MEMS devices are achieved using a cap wafer that is formed using two silicon wafers, where one wafer has precise grating/moth-eye structures on both sides of a double-sided polished wafer for improved transmission of over 80% in the long-wave infrared (LWIR) wavelength region without the need for an AR coating, while the other wafer is used to form a cavity. The two wafers are bonded using Au-In transient liquid phase (TLP) bonding at low temperature to form the cap wafer, which is then bondelectrical and Electronics d to the sensor wafer using glass frit bonding at high temperature to activate the getter inside the cavity region. The bond quality is assessed using three methods, including He-leak tests, cap deflection, and Pirani vacuum gauges. Hermeticity is confirmed through He-leak tests according to MIL-STD 883, yielding values as low as 0.1 × 10-9 atm·cc/s. The average shear strength is measured as 23.38 MPa. The package pressure varies from 133-533 Pa without the getter usage to as low as 0.13 Pa with the getter usage.

Investigation of Vapor HF Sacrificial Etching Characteristics Through Submicron Release Holes for Wafer-Level Vacuum Packaging Based on Silicon Migration Seal

Vapor hydrogen fluoride (vHF) sacrificial SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{2}$</tex-math> </inline-formula> etching is a crucial process for wafer-level packaging based on silicon migration seal (SMS) technology. In this study, by using test samples with several kinds of test patterns and structures, the characteristics of vHF etching through release holes with a diameter of 0.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m were investigated. The results showed that through-hole etch rate had some dependence on the number and distribution of release holes, distance from the release holes, and dimension of sealed cavity, which is much different from normal vHF etching. The stiction problem in such a special case was also tested by releasing cantilever structures of different length. They were more likely to bend during through-hole etching than during normal etching. This work reveals the role of the water as both a by-product and catalyst during through-hole vHF etching. The results of this study provide important design guidelines for SMS-based MEMS packaging as well as other similar vacuum packaging technology and improve the understanding of vHF etching mechanisms. 2023-0065

Design of Wafer Level Solder Seals – A Surface Energy Perspective

Wafer level vacuum packaging of quartz resonators and microelectromechanical system (MEMS) inertial sensors and RF switches have been successfully demonstrated by a number of investigators. The majority of these devices were sealed using reflow of gold-tin solder because of its superior hermeticity and benign processing conditions as compared to seals made using glass frit or anodic bonding. These successes have motivated efforts to integrate multiple sensors and active silicon devices within the same package to achieve improved performance and further reduce system size and cost. Sealing these large, heterogeneous assemblies at wafer level presents a more challenging problem than sealing small individual sensors, primarily due to wafer bow and irregularities in the seal surfaces. Wafer bow has been addressed in sealing wafers of individual sensors by plating metal stops adjacent to the seal rings, which allow the wafers to be pressed together to flatten the seal areas during bonding. This strategy cannot always be applied to sealing system devices because the amount of wafer bow is greater than that associated with more uniform wafers of sensors and the larger area of system devices increase the residual stress on the solder seal. An alternative approach to pressing wafers flat throughout the bond process would be to relax the force during reflow and allow the solder to bridge the nonplanar interface. We have used analytical and numerical calculations to investigate the interplay between seal width, height and shape of the seal gap, and solder volume associated with this bonding strategy. A set of soldering experiments were conducted on test articles that allowed us to independently vary these parameters to evaluate our model predictions.

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Wafer level hermetic bonding and packaging using recrystallized parylene

This work reports a wafer-level vacuum packaging technique for microelectromechanical system (MEMS) using recrystallized parylene material as a bonding layer. The effect of thermal annealing on the crystallinity of the parylene surface was demonstrated. The low-temperature, stable, homogeneous, and defect-free recrystallized parylene is found as an excellent bonding material for hermetic packages, suitable for the packaging of MEMS sensors. The material’s recrystallization improves its capabilities as a moisture and air barrier. The mechanical stability of the bond interface was also investigated by measuring the package’s tensile and shear strength. In the absence of a vacuum bonding tool, a Ti getter was integrated into the cavity of the glass capping wafer to create the vacuum and test the hermeticity. The MEMS silicon Pirani gauge was used to monitor the pressure changes inside the sealed cavity. After the getter activation, it was observed that there was a decrease in the pressure from atmospheric pressure to 0.2 mbar for the first few days; after that, no noticeable change was observed. The hermeticity of the packaged device was examined, and the vacuum level inside the package remained the same for the last 70 d. The recrystallized parylene bonded micro package shows better hermeticity than the non-recrystallized parylene micro package.

Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances

We present the novel 3D wafer-level vacuum packaging technology for MEMS, which only needs two masks and is realized by Au-Si eutectic bonding with a low-resistivity Si Cap wafer. Wherein, Au-Si bonding pads and rings are formed to accomplish vertical interconnects and a vacuum package respectively. Applied to resonators with two typical substrate wafers of Si and Glass, this 3D package structure has further gone through the systemic characterizations. Specifically, the high-reliable mechanic strengths of device packages are revealed from Au-Si bonding strengths measured as about 20 MPa in tensile tests. Based on analyzing parasitic capacitance networks in device packages, the feed-through effect in resonance tests can be effectively relieved by grounding on each Si layer in device package structures (i.e. the parasitic capacitance reduced from the level of pF to fF). By resonance tests, it is found that increasing the degassing duration (30 min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 60$ </tex-math></inline-formula> min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> min) is beneficial for improving package vacuum degrees as well as consistencies (69% within 4–30 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 88$ </tex-math></inline-formula> % within 0.6-1.2 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 85$ </tex-math></inline-formula> % within 0.6-0.8 kPa), and hermetic package yields (73% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 86$ </tex-math></inline-formula> % <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> %). Besides, device packages are verified to have good long-term stability by monitoring quality factor variations in 6 months. Overall, this proposed 3D packaging technology has extensive application prospects in various MEMS devices due to its inherently-simple process, low capacitive feed-through effect, and fine package performances. Also, test results provide instructions on the realization of low-parasitic-capacitance signal interfaces and the optimization of wafer-level vacuum package processes.

A Wafer-Level Vacuum Packaged MEMS Disk Resonator Gyroscope With 0.42°/h Bias Instability Within ±300°/s Full Scale

This article reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk of 0.05°/√h and bias instability of 0.42°/h within a full scale of ±300°/s, making it a very promising solution for angular measurement in high-end industrial applications.

Study of the Absorption of Electromagnetic Radiation by 3D, Vacuum-Packaged, Nano-Machined CMOS Transistors for Uncooled IR Sensing.

There is an ongoing effort to fabricate miniature, low-cost, and sensitive thermal sensors for domestic and industrial uses. This paper presents a miniature thermal sensor (dubbed TMOS) that is fabricated in advanced CMOS FABs, where the micromachined CMOS-SOI transistor, implemented with a 130-nm technology node, acts as a sensing element. This study puts emphasis on the study of electromagnetic absorption via the vacuum-packaged TMOS and how to optimize it. The regular CMOS transistor is transformed to a high-performance sensor by the micro- or nano-machining process that releases it from the silicon substrate by wafer-level processing and vacuum packaging. Since the TMOS is processed in a CMOS-SOI FAB and is comprised of multiple thin layers that follow strict FAB design rules, the absorbed electromagnetic radiation cannot be modeled accurately and a simulation tool is required. This paper presents modeling and simulations based on the LUMERICAL software package of the vacuum-packaged TMOS. A very high absorption coefficient may be achieved by understanding the physics, as well as the role of each layer.

A High Q-Factor Outer-Frame-Anchor Gyroscope Operating at First Resonant Mode.

Disc gyroscope manufactured through microelectromechanical systems (MEMS) fabrication processes becomes one of the most critical solutions for achieving high performance. Some reported novel disc constructions acquire good performance in bias instability, scale factor nonlinearity, etc. However, antivibration characteristics are also important for the devices, especially in engineering applications. For multi-ring structures with central anchors, the out-of-plane motions are in the first few modes, easily excited within the vibration environment. The paper presents a multi-ring gyro with good dynamic characteristics, operating at the first resonant mode. The design helps obtain better static performance and antivibration characteristics with anchor points outside of the multi-ring resonator. According to harmonic experiments, the nearest interference mode is located at 30,311 Hz, whose frequency difference is 72.8% far away from working modes. The structures were fabricated with silicon on insulator (SOI) processes and wafer-level vacuum packaging, where the asymmetry is 780 ppm as the frequency splits. The gyro also obtains a high Q-factor. The measured value at 0.15 Pa was 162 k, which makes the structure have sizeable mechanical sensitivity and low noise.

Waferlevel Vacuum Packaged Microscanners: A High Yield Fabrication Process for Mobile Applications

Packaging of MEMS is an important expense factor within the production costs and, to ensure mass producibility, the packaging has to be performed on a waferlevel. While for inertial MEMS this is state of the art, it has not yet been reported for scanning micromirrors. Therefore, Fraunhofer ISIT has developed a process technology based on two 30 μm thick epitaxially deposited polysilicon layers for the manufacturing of waferlevel vacuum packaged MEMS scanning mirrors. It allows the fabrication of vertically stacked combdrives for out-of-plane mirror operation and a low damping environment for the reduction of needed driving signals. An anodically bonded structured glass wafer seals the devices at the front side, while an Au-Si eutectically bonded silicon wafer with an integrated 400 nm thick Ti getter layer is used to seal the devices from the backside. The measurement of the quality factor allows the estimation of the internal cavity pressure of sealed devices, which is in the range of 10-3 mbar.Waferlevel measurements showed that the fabrication process reaches a high mechanical yield of Ym = 95%. Vacuum packaged devices needed 6V driving voltage to reach a total optical scan angle of above 50°.

3중 접합 공정에 의한 MEMS 공진기의 웨이퍼레벨 진공 패키징

3중 접합 공정에 의한 MEMS 공진기의 웨이퍼레벨 진공 패키징

Wafer-Level Vacuum-Packaged Translatory MEMS Actuator with Large Stroke for NIR-FT Spectrometers.

We present a wafer-level vacuum-packaged (WLVP) translatory micro-electro-mechanical system (MEMS) actuator developed for a compact near-infrared-Fourier transform spectrometer (NIR-FTS) with 800–2500 nm spectral bandwidth and signal-nose-ratio (SNR) > 1000 in the smaller bandwidth range (1200–2500 nm) for 1 s measuring time. Although monolithic, highly miniaturized MEMS NIR-FTSs exist today, we follow a classical optical FT instrumentation using a resonant MEMS mirror of 5 mm diameter with precise out-of-plane translatory oscillation for optical path-length modulation. Compared to highly miniaturized MEMS NIR-FTS, the present concept features higher optical throughput and resolution, as well as mechanical robustness and insensitivity to vibration and mechanical shock, compared to conventional FTS mirror drives. The large-stroke MEMS design uses a fully symmetrical four-pantograph suspension, avoiding problems with tilting and parasitic modes. Due to significant gas damping, a permanent vacuum of ≤3.21 Pa is required. Therefore, an MEMS design with WLVP optimization for the NIR spectral range with minimized static and dynamic mirror deformation of ≤100 nm was developed. For hermetic sealing, glass-frit bonding at elevated process temperatures of 430–440 °C was used to ensure compatibility with a qualified MEMS processes. Finally, a WLVP MEMS with a vacuum pressure of ≤0.15 Pa and Q ≥ 38,600 was realized, resulting in a stroke of 700 µm at 267 Hz for driving at 4 V in parametric resonance. The long-term stability of the 0.2 Pa interior vacuum was successfully tested using a Ne fine-leakage test and resulted in an estimated lifetime of >10 years. This meets the requirements of a compact NIR-FTS.

Layer Configurations for Al-Ge Eutectic Wafer Bonding

Introduction Heterogeneous integration between CMOS and MEMS devices can be realized by using Al-Ge which are compatible materials in both fabrication environments. Al is widely used in the CMOS-industry and does not involve any contamination risk in contrast to other eutectic systems like Au-Si[1]. Si-Ge is also widely used to augment transistor switching speed [2]. The eutectic reaction for Al-Ge takes place around 420oC, which is CMOS-compatible[3], [4].The limitation of the Al-Ge system is the need for removal of the surface oxides. It was previously reported that Ge can be deposited on top of Al using evaporation or sputtering without vacuum-break [4]. This prevents oxide formation on the Al layer. By contrast, GeO2 is easy to remove with a dilute-HF dip [5]. The current work investigates using a single layer or dual layers of Al and Ge for bonding. Depositing single layers is advantageous since it enables patterning by dry etch and avoids the need for a lift-off process. The layers are deposited in separate tools, so oxide formation is expected. The effect of the presence of the oxide layers will be investigated. Method Al and Ge layers are deposited on 200 mm wafers with 500 nm thermal oxide. Thicknesses are matched to eutectic composition. (300 nm Ge and 500 nm Al) The wafers are bonded and then analyzed using scanning acoustic microscopy (SAM) and cross-sectional scanning electron microscopy (X-SEM). Results and discussion The first group of wafers are prepared with a single layer of Al and Ge on either substrate while the second group has a double layer of either Al on top of Ge or Ge on top of Al. All wafers are joined by using forming gas pre-treatment at 390oC, 15 min of solid state inter-diffusion at 410oC followed by bonding for 30 min at 450oC with 25 kN of force. The bonding recipe is illustrated in figure 1. The wafers are analyzed using SAM and X-SEM. The SAM results are shown in figure 2.In figure 2.a the result of the single layer configuration bond is visible. Micro-voids are visible in the center. The outer region has larger voids. The X-SEM image of the bonding interface confirms the presence of small voids, as shown in figure 3. The formation of the eutectic in the single layer configuration is only possible where the two wafers are in contact. Non-uniformity and roughness could be preventing full contact and result in voids.The SAM result of the Al on top of Ge double layer configuration bond is shown in Figure 2.b, the outer region is mostly unbonded. The bonding interface is clearly visible on the X-SEM image, as shown in figure 4. There is no interface between the Al and the Ge layer visible. The native oxide on top of the Al layer could be preventing the two sides from mixing but the Ge oxide layer does not seem to hinder the eutectic formation.The SAM image of the Ge on top of Al configuration bond is shown in figure 2.c. The wafer looks well bonded. X-SEM reveals a triple layer structure. (see figure 5) The bond interface is clearly visible and additionally two thinner interfaces are visible. These could be the remainder of the native Al-oxide. Conclusion Three configurations of Al-Ge eutectic bonds were investigated using SAM and X-SEM. The highest bond uniformity is obtained with Ge being the top layer prior to bonding. The presence of the oxide layers could be preventing the mixing of the eutectic across the bonding interface. In this regard especially the Al-oxide seems problematic.[1] B. Pathangey, L. D. McCarthy, and D. C. Skilbred, “Effect of metal contaminants in pre-gate oxide cleans for sub-100-nm devices,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 4, pp. 631–638, Dec. 2005, doi: 10.1109/TDMR.2005.861161.[2] M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, “Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 97, no. 1, p. 011101, Jan. 2005, doi: 10.1063/1.1819976.[3] H. Takeuchi, A. Wung, X. Sun, R. T. Howe, and T.-J. King, “Thermal Budget Limits of Quarter-Micrometer Foundry” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2081–2086, Sep. 2005, doi: 10.1109/TED.2005.854287.[4] A. Hilton and D. Temple, “Wafer-Level Vacuum Packaging of Smart Sensors,” Sensors, vol. 16, no. 11, p. 1819, Oct. 2016, doi: 10.3390/s16111819.[5] B. Onsia et al., “The Influence of Wet Treatments on the Germanium Wafer Surface,” Solid State Phenom., vol. 103–104, pp. 27–30, Apr. 2005, doi: 10.4028/www.scientific.net/SSP.103-104.27. Figure 1

Non-Imaging Digital CMOS-SOI-MEMS Uncooled Passive Infra-Red Sensing Systems

This paper presents a novel non-imaging digital passive Infra-Red (PIR) sensing system using a CMOS-SOI-MEMS transistor as the thermal sensor, which replaces the traditional pyroelectric sensors and outperforms thermopiles. The mosaic sensors, which are manufactured by nano-fabrication methods in standard FABs, exhibit enhanced performance and robust manufacturing on wafer level processing and vacuum packaging. Mirror optics instead of Fresnel plastic lenses provides enhanced performance at low-cost. The essential aspects of the design of the mirrors for curtain sensors and presence sensors are presented. The overall measured performance for detecting human targets at extended ranges and hot spots detection are reported. The overall performance of the sensing systems indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things (IoT) and mobile applications.

Effect of Au Film Thickness and Surface Roughness on Room-Temperature Wafer Bonding and Wafer-Scale Vacuum Sealing by Au-Au Surface Activated Bonding.

Au-Au surface activated bonding (SAB) using ultrathin Au films is effective for room-temperature pressureless wafer bonding. This paper reports the effect of the film thickness (15–500 nm) and surface roughness (0.3–1.6 nm) on room-temperature pressureless wafer bonding and sealing. The root-mean-square surface roughness and grain size of sputtered Au thin films on Si and glass wafers increased with the film thickness. The bonded area was more than 85% of the total wafer area when the film thickness was 100 nm or less and decreased as the thickness increased. Room-temperature wafer-scale vacuum sealing was achieved when Au thin films with a thickness of 50 nm or less were used. These results suggest that Au-Au SAB using ultrathin Au films is useful in achieving room-temperature wafer-level hermetic and vacuum packaging of microelectromechanical systems and optoelectronic devices.

Effect of Environment on Activation and Sorption of Getter Alloys and Multilayers for Hybrid Wafer-level Vacuum Packaging

Effect of Environment on Activation and Sorption of Getter Alloys and Multilayers for Hybrid Wafer-level Vacuum Packaging

In situ electrical characterization of YxTiy getter thin films during thermal activation

Transition metals alloys are the most studied getter films for wafer-level vacuum packaging of MEMS. In this work we investigated yttrium and YxTiy alloys films that could possibly overcome the limitations of usual getter materials, i.e. reversible sorption of hydrogen and low sorption ability for hydrocarbon gases. As a preliminary step towards this objective, properties of (co-)evaporated yttrium and YxTiy films were analyzed by SEM, EDS, XPS and in-situ sheet resistance measurements before, after and/or during annealing in vacuum. As deposited and annealed films have a small grain size and a columnar structure. It is shown that yttrium and YxTiy films can be activated after 1 hour of annealing in vacuum at 250 °C if the Y-content is larger than ∼9 %. These results are promising for the use of Y-based films as low temperature getters for vacuum packaging.

Hermetic Sealant Material Possibilities for IR Sensor Packaging

Hermeticity is one of the most critical issues for infrared (IR) sensor packages, since any leakage will impair the functionality of the device. The issues associated with the premature failure of hermetic sealants were studied in detail, both by simulation as well as by experimentation. Alternate prospective hermetic sealant candidates for transistor outline IR sensor packages were identified and evaluated. Hermetic sealant options for wafer-level IR sensor packaging were also investigated, which involves wafer-level hermetic cum vacuum packaging. Metallic hermetic sealant is preferred for this approach, since it facilitates integration with the getter material. However, the primary challenge encountered here is the requirement of high processing temperature for the getter activation. An activated getter adsorbs active gases inside the volume of the packages, resulting in lower internal pressure. It was determined that appropriate micro-alloying of the getter is required to minimize the getter activation temperature. This is achieved by selective micro-alloying of the getter material, which induces more grain boundaries and thereby promotes in-depth diffusion even at lower activation temperature. Integration of getter material with all three different types of metallic wafer-level bonding mechanisms was investigated. This includes eutectic, diffusion and transient liquid-phase bonding mechanisms. Selection of an appropriate bonding mechanism and integration scheme depends on the corresponding structure, layout and temperature rating of the specific IR sensor devices.

Numerical and Experimental Investigation into LWIR Transmission Performance of Complementary Silicon Subwavelength Antireflection Grating (SWARG) Structures

This paper presents a detailed comparison between the long wave infrared (LWIR) transmission performances of binary, silicon based, structurally complementary pillar and groove type antireflective gratings that can be used for wafer level vacuum packaging (WLVP) of uncooled microbolometer detectors. Both pillar and groove type gratings are designed with various topological configurations changing in various period sizes (Λ) from 1.0 μm to 2.0 μm, various heights/depths (h) from 0.8 μm to 1.8 μm, and various pillar/groove width-to-period (w/Λ) ratios from 0.6 to 1.0. The transmission performance of gratings is simulated with a hybrid simulation technique based on the modification of the reflection term within the Fresnel transmission equation, which combines both numerical and analytical approaches in a unique way for the first time in literature. Simulation results are experimentally verified with 19 different fabricated structures where a spectral agreement is achieved with an absolute root-mean-square (RMS) error less than 5.4% within the subwavelength (SW) regime, proving the effectiveness of the proposed hybrid technique. These results show first time in the literature that both pillar and groove type silicon based gratings present similar spectral IR transmission characteristics, and they are also structurally complementary when optimum configurations are employed to maximize the transmission.

Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages

Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25- $\mu \text{m}$ -thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold–aluminum (Au–Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 $\mu \text{m}$ , respectively. Despite the small sealing footprint, the Si caps with 9- $\mu \text{m}$ -wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than ${2.8}\times {10}^{-14}$ mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 $\mu \text{m}$ by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip–chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages. [2018-0257]