Wafer Interconnects Research Articles

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method.

In advanced packaging technology, the micro bump has become an important means of chip stacking and wafer interconnection. The reliability of micro bumps, which plays an important role in mechanical support, electrical connection, signal transmission and heat dissipation, determines the quality of chip packaging. Surface morphological defects are one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. In this paper, the electrodeposition process of preparing gold bumps is simulated at the atomic scale using the Kinetic Monte Carlo method. The differences in surface morphology and roughness of the plated layer are studied from a microscopic perspective under different deposition parameters. The results show that the gold micro bumps prepared by electrodeposition have better surface quality under conditions of lower deposition voltage, lower ion concentration and higher plating temperature, which can provide significant guidance for engineering applications.

Manufacturing and DC characterization of conductive through wafer via for MEMS applications

In this paper we demonstrate a method to manufacture low resistance through wafer interconnections using gold as the conductive layer. 200 μm thick high resistivity (HR) Si wafers were used and 100 μm diameter through wafer via (TWV) were manufactured by dry etching. The conductive layer was manufactured first by depositing TiAu (DC sputtering) on both sides, followed by gold electroplating to reach the desired thickness. Finally, conductive TWV were sealed by using benzocyclobutene removal. DC measurements have shown a resistance of about 48.5 mΩ/via.

An Investigation of Processes for Glass Micromachining.

This paper presents processes for glass micromachining, including sandblast, wet etching, reactive ion etching (RIE), and glass reflow techniques. The advantages as well as disadvantages of each method are presented and discussed in light of the experiments. Sandblast and wet etching techniques are simple processes but face difficulties in small and high-aspect-ratio structures. A sandblasted 2 cm × 2 cm Tempax glass wafer with an etching depth of approximately 150 µm is demonstrated. The Tempax glass structure with an etching depth and sides of approximately 20 μm was observed via the wet etching process. The most important aspect of this work was to develop RIE and glass reflow techniques. The current challenges of these methods are addressed here. Deep Tempax glass pillars having a smooth surface, vertical shapes, and a high aspect ratio of 10 with 1-μm-diameter glass pillars, a 2-μm pitch, and a 10-μm etched depth were achieved via the RIE technique. Through-silicon wafer interconnects, embedded inside the Tempax glass, are successfully demonstrated via the glass reflow technique. Glass reflow into large cavities (larger than 100 μm), a micro-trench (0.8-μm wide trench), and a micro-capillary (1-μm diameter) are investigated. An additional optimization of process flow was performed for glass penetration into micro-scale patterns.

Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device

In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft HFSS <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around 1.9 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the ldquoY-shapedrdquo through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.

Via-in-pixel design of truly 2D extendable photodiode detector for medical CT imaging

This paper presents a new design of the silicon-based photodiode detector for medical imaging, especially for the X-ray computed tomography applications. The new structure of the photodiode includes a conventional front-illuminated photodiode and a through wafer interconnection. Moreover, the through wafer interconnection is integrated into the photodiode by being placed inside the active area of the photodiode. This new structure is called via-in-pixel design. Truly 2D photodiode detector can be designed with maximum free space or minimum gap between each two photodiode elements by using the via-in-pixel design. In addition, 2D photodiode detector arrays can be constructed by tiling more edgeless detectors. In the paper, the via-in-pixel photodiodes were demonstrated and the performances were measured. Together with the measurement data, a quasi-3D device simulation was performed to disclose the electrical characteristics of the via-in-pixel photodiode by using Synopsis Advanced TCAD software. The results show that the via-in-pixel design of the photodiode detector can either meet or exceed the medical imaging requirements.

Through Wafer Interconnects - A Technology not only for Medical Applications

AbstractThe foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications. The front to back-side contact allows the four-side buttable chip placement of the already large chips (20mm × 22mm2). The TWI technology allows an interconnection for chips up to 280μm thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. The production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280μm), which are passivated and filled with doped poly-silicon. The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes. The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature back-side process starting with wafer thinning down to 280μm or less to open the implemented TWI structure from the back-side. The thickness may be selected depending on the target application. A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the solder ball placement, or similar bond connections.The special process flow opens a variety of applications which benefit from the full CMOS compatible processing and the accessible front-side.

Through Wafer Interconnects for 3-D Packaging

ABSTRACTSemiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.

Through Wafer Interconnects - A Technology not only for Medical Applications

AbstractThe foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications. The front to back-side contact allows the four-side buttable chip placement of the already large chips (20mm × 22mm2). The TWI technology allows an interconnection for chips up to 280μm thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. The production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280μm), which are passivated and filled with doped poly-silicon. The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes. The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature back-side process starting with wafer thinning down to 280μm or less to open the implemented TWI structure from the back-side. The thickness may be selected depending on the target application. A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the solder ball placement, or similar bond connections.The special process flow opens a variety of applications which benefit from the full CMOS compatible processing and the accessible front-side.

Curled micro-cantilevers using benzocyclobutene polymer and Mo for wafer level probing

We verified by experiments that only the compressive stressed Mo layer was enough to deflect after release because self-stress gradient originated from strain difference along thickness. This circumstance normally occurred in the sputtered thick films as the crystallography/microstructure difference along the thickness. The deflection height and contact-force at the fully compressed state were found as 128 μm and 231 μN, respectively, in conditions of 2.48 μm thickness and 500 μm length of Mo single layer. These figures are enough to apply to the wafer level testing and interconnects. In addition, composite probe, consisting of Mo metal film and BCB polymer, was analyzed numerically and fabricated for the first time in order to increase the contact-force/stiffness, and for electrical isolation in high frequency devices testing. However, the resultant composite probe showed weak structural properties due to the low stress of BCB and poor adhesion between Mo and BCB. The stress control of BCB layer and process modification for good adhesion were found as solutions for applicable composite cantilever-type probe fabrication.

The future of gold in electronics

Gold-based materials have been a mainstay of the electronics and semiconductor industry since the physics was just a laboratory curiosity. Gold is the workhorse material in wire bond, flip chip and off wafer interconnections due to its corrosion resistance, ability to form metallurgical bonds by soldering or cold welding, and ease of fabrication. As the electronics and semiconductor industries grew, so did the use, of gold in spite of the feature size reduction so elegantly demonstrated in Moore's law. However, several revolutions in the Silicon miracle are threatening gold's place as the material of choice. Although cost is always an issue, the limitations are associated with the chemistry of gold based alloys. Will gold remain? Emerging requirements of bioelectronics, photonics and power requirements in conventional device represent new opportunities for gold to shine. Additionally, as the world market demand for electronic, semiconducting, bio-electronic and photonic technology increases, given the right technology, gold still can provide value proposition.

Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection

Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting.

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.

Multilevel interconnections for wafer scale integration

Multilevel interconnections (MLIC) are the key to successful wafer scale integration (WSI). In this paper, we present a review of various approaches used in the implementation in MLIC to both monolithic WSI and wafer scale hybrid packaging. Electrical interconnections using both thin (micron dimensions) and thick (tens of microns dimensions) dielectric and metal films are discussed from a performance standpoint. The advantages of the thick film approach for realizing transmission line performance is indicated. Techniques for implementing thick electrical interconnections such as plate‐up, via etching and lift‐off, are described. This treatment includes silicon‐die‐on‐wafer, silicon‐die‐on‐ceramic, and GaAs‐on‐silicon wafer hybrids. Fabrication approaches which have been explored by several research groups are compared. Some projections concerning yield of the wafer interconnections are calculated. Finally, a brief examination of some potential approaches to three‐dimensional stacking of wafers is made, including two‐sided population of wafers.

A means of reducing custom LSI interconnection requirements

Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective circuits that naturally occur on such large circuit arrays, it has been necessary to customize each wafer's interconnection mask to its unique yield pattern. The authors examine in detail a means of using each mask set for perhaps several unique wafers, thus providing important custom routing and mask generation cost savings. In the case of pad relocation, only a single mask then comprises the entire custom mask set for several wafer arrays.