Direct Wafer Bonding Research Articles

Direct Wafer Bonding of 128° Y-Cut LiNbO3: A Pathway to High Frequency (50 GHz) Filter Applications

In this work, room temperature direct wafer bonding of complementarily oriented 128° Y-cut LiNbO3 substrates is achieved with an interfacial layer less than 1 nm thick. This compares well to commercially available structures with thickness of 3 nm and this interfacial width is particularly important for eventual multilayer bonding sequences with each layer on the order of only tens of nm. The (0114) indices describe the surface plane of 128° Y-cut LiNbO3 wafers; and the wafers were bonded such that their in-plane [055.12] directions were antiparallel. Due to its trigonal crystal structure, this zone axis has 1-fold symmetry and therefore is crystallographically distinguishable from either side of the bonded interface. The wafers were cleaned with standard cleaning protocols and subsequently brought in contact face-to-face and bonded. The bonding was performed in ambient atmosphere and the applied pressure was on the order of ~kPa. The bonded pair was then annealed at 200 °C for 10 h in order to strengthen the bond, which is fully compatible with exfoliation of He-implanted LiNbO3 layers. Limited literature has been reported for direct bonding of LiNbO3 to LiNbO3 and even fewer investigate the atomic structure of the bonded interface.1-3 Tomita et al., observe structurally disordered bonded interfaces after annealing at high temperatures (up to 1000 °C). High resolution transmission electron microscopy of the interface presented here reveal an abrupt interface (≤ ~1 nm) and a φ X-ray scan has confirmed a relative twist of ~180° between substrates. This is a follow-up work for what has previously been achieved by our group demonstrating direct wafer bonding and layer transfer of LiNbO3 to substrates such as sapphire and oxidized silicon.4 Combining these latest results will enable the fabrication of a multilayer structure of complementarily oriented LiNbO3 thin films on a sapphire substrate, which has applications for high frequency (50 GHz) filters. Similar structures using a different LiNbO3 orientation (X-cut) have been demonstrated to maintain high quality factor (Q) at 15.8 GHz.5 The authors would like to acknowledge the support from DARPA through the Compact Front-end Filters at the ElEment-level (COFFEE) program.[1] Tulli, D., Janner, D. and Pruneri, V., “Room temperature direct bonding of LiNbO3 crystal layers and its application to high-voltage optical sensing.” Journal of Micromechanics and Microengineering, 21(8), p.085025 (2011).[2] Tomita, Y., Sugimoto, M., & Eda, K., “Direct bonding of LiNbO3 single crystals for optical waveguides.” Applied physics letters, 66(12), 1484-1485 (1995).[3] Berini, P., Mattiussi, G., Lahoud, N. and Charbonneau, R., “Wafer-bonded surface plasmon waveguides.” Applied physics letters, 90(6), p.061108 (2007).[4] Liao, M. E., Matto, L., Huynh, K., and Goorsky, M. S., “Direct Wafer Bonding of 128° Y-Cut LiNbO3 to Sapphire”. WaferBond ’22, Presentation (2022).[5] Lu, R., and Gong, S., 2021 Joint Conf. EFTF/IFCS, 1 (2021). Figure 1

Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization

There are different requirements for the production process and the final product of SiC-SiC wafer bonding. The manufacturing of devices that are sensitive to high temperature processing – due to broadened doping profiles and induced thermal stresses – requires room temperature bonding with high bond strength, while for electrical devices, it is mandatory that the bonding interface with a thin amorphous layer is oxide-free.[1] Reduced complexity of processes is also an important point for the final production. Hence, the goal of this work was to perform and characterize direct bonding of SiC-SiC without any added/deposited bonding layer. This type of bonded SiC wafers can be used for power electronics such as for the fabrication of traction inverter for automotive applications, DC/DC converter, on board charger or charging station.[2]For the wafer bonding processes standard 100 mm 4H SiC wafers were bonded with their Si-terminated faces in order to fabricate oxide-free bonds. The wafer bonding process was performed using the EVG ComBond® system: first the native oxides from both wafer surfaces were removed using an ion beam sputtering process, followed by the transfer of both wafers to the bonding process station operated in ultra-high vacuum (UHV) to significantly retard the oxidation process. Finally, the bonding process was performed at room temperature (RT).The goal of this study was to demonstrate the feasibility of the bonding process and to gain insight on the surface chemistry after activation. The investigations covered three areas: incoming inspection of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. In the case of single wafers, the focus of the incoming inspection was on whether the wafers fulfill the requirements of wafer bonding, and on the characterization of activated wafers to measure the surface modifications. Atomic force microscopy (AFM), white light interferometry (WLI) and spectroscopic ellipsometry (SE) were used to determine the surface roughness, the wafer topography and the surface layer structure, respectively. All three parameters are essential for successful RT SiC-SiC wafer bonding. The change of the surface chemistry was investigated by angle resolved x-ray photoelectron spectroscopy (AR-XPS). The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy (SAM) measurements (Fig. 1) as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy (X-TEM) showed a bonding interface with a thin amorphous layer and no noticeable additional oxygen containing layer (Fig. 2). In order to gain quantitative elemental distributions of oxygen and argon, energy dispersive x-ray spectroscopy (EDXS) was applied.The work reported is a demonstration of the capability of the different characterization methods regarding SiC-SiC wafer bonding. Future work will focus on the investigation of the bonded interface characteristics in the function of the bonding process parameters and the annealing conditions.[1] F. Mu, M. Fujino, T. Suga, Y. Takahashi, H. Nakazawa and K. Iguchi, "Wafer bonding of SiC-SiC and SiC-Si by modified surface activated bonding method" 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), Kyoto, Japan, 2015, pp. 542-545, doi: 10.1109/ICEP-IAAC.2015.7111073.[2] Tsunenobu Kimoto, "Material science and device physics in SiC technology for high-voltage power devices" Jpn. J. Appl. Phys. 54 040103 (2015), doi: 10.7567/JJAP.54.040103. Figure 1

Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization

In this study, the feasibility of oxide-free room temperature wafer bonding process was demonstrated for 4H-SiC wafers with in situ surface oxide removal. The investigations covered three areas: incoming metrology of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. Incoming wafers were inspected whether they fulfill the requirements of wafer bonding, and activated wafers were characterized to measure the surface modifications. The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy measurements as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy was used to investigate the amorphous layer at the bonding interface. The work reported is a demonstration of the capability of different characterization methods regarding SiC-SiC wafer bonding.

(Invited) Optoelectronic and 3D Applications with Die to Wafer Direct Bonding: From Mechanisms to Applications

—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.IntroductionSOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology available in many industrial microelectronic factories. Direct bonding of 200 mm or 300 mm silicon wafers are nowadays well mastered. For many innovative applications, it could be interesting to introduce new materials like InP, AsGa, GaN on a silicon platform. Heterostructure bonding then needs to be developed. This could be done with wafer-to-wafer bonding. However, wafers made of these new materials usually have diameters much smaller than that of silicon wafers, especially if CMOS are required on the silicon wafers. Indeed, advanced CMOS devices are nowadays only available on 200/300 mm silicon wafers. Even if the bonding of a small wafer on a bigger one is easily feasible, the silicon surface lost will be detrimental to the cost of the device. Moreover, usually, a very small surface of the new material is needed on the silicon wafer. With a wafer-to-wafer bonding (W2W), the new material surface loss will be quite important. Die-to-wafer (D2W) bonding is thus the solution to both issues in order to put only a small amount of new material where it is needed and populate all the active area on silicon wafers.D2W is also interesting in hybrid bonding with silicon wafers. Indeed, D2W enlarges design rules to mix different technologies (material, dies size) on the same bottom wafer while enabling high density of copper interconnects.. Hybrid D2W is then foreseen as being the next step for hybrid bonding in order to widen its application field.ResultsStarting with the well know fundamental mechanisms of silicon dioxide bonding [1] as well as copper and hybrid surface bonding [2], D2W bonding behavior will be discussed. Some specific features indeed have to be taken into account for die bonding. For instance, all the edge effects, during and after the bonding or the annealing, have a great impact on the bonding energy as well as on the interface defectivity. Moreover, specific bonding techniques using for instance liquid water films can be used only in D2W bonding. If these specific features are under control, very innovative structures can be obtained. It is possible for instance to bond small 3mm*3mm InP dies onto 200mm silicon photonic wafers as shown in Fig.1a [3]. Moreover, hybrid bonding interfaces can also be obtained between 6mm*4mm dies and a 300mm wafer as shown in Fig.1b. Obviously, alignment in mandatory during hybrid bonding. This can be obtained thanks to a die to wafer bonder. However, innovative technologies such as capillary assisted self-assembly can also be really interesting [4 -7]. The electrical characterization of the D2W hybrid bonding connection will be also discussed, showing roughly the same good results as for W2W hybrid bonding.AcknowledgmentThis work was funded thanks to the French National program “Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05.References 1 F. Fournel, et al., ECS J. Solid State Sci. Technol. 4, P124 (2015). 2 L.D. Cioccio, et al., J. Electrochem. Soc. 158, P81 (2011). 3 B. Szelag et al., Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform, IEEE J. Sel. Top. Quantum Electron., In Press (2019). 4 A. Jouve, et al., ECTC (2019). 5 T. Fukushima, et al., in 2011 IEEE 61st Electron. Compon. Technol. Conf. ECTC (2011), pp. 2050–2055. 6 E. Bourjot, et al., ECTC(2021) Figure 1

Stress Engineering in Germanium-Silicon Heterostructure Using Surface Activated Hot Bonding

The manufacturing of heterostructures is interesting in fields such as photonics(1), solar energy production(2) and quantum technologies(3). This paper, dedicated to germanium on silicon heterostructure manufacturing and stress engineering, builds up on Ref. (4) findings.We are using the differences in terms of coefficients of thermal expansion (CTE) between germanium and silicon, to induce a tensile stress in a thin germanium layer transferred by the Smart CutTM [1] technique onto a silicon substrate. In this approach, a bulk germanium wafer is directly bonded on a bulk silicon wafer, using surface activated bonding (SAB)(5,6). Process integration advantages are the low defect density of bulk germanium and the tensile stress that can be tuned using the bonding temperature.The adherence of SAB was high during bonding at relatively high temperatures (~250°C). Without any further heat treatment, the adherence was found to be 3500mJ/m2 by the double cantilever beam method (under prescribed displacement control and in an anhydrous atmosphere). This remarkable adherence prevented the Ge/Si heterostructure from sliding, debonding and cracking (7). The CTE difference could thus generate a large amount of tensile stress during the heterostructure cooling and splitting steps.First of all, using finite elements simulation, a model was designed to predict the bow and the in-plane internal stress after bonding and cooling of the heterostructure. Thanks to it, we could also evaluate those two values after layer transfer (splitting step). This numerical approach was more accurate than the former analytic method (Timoshenko), which did not include the non-linearity of CTE with temperature and for large displacements. Figure 1 shows the bow and the in-plane stress expected for a bonding at 250°C of, respectively, a Si/Si homostructure (Figure1.a) and a strained Ge/Si heterostructure (Figure1.b), when cooled down to room temperature. The former is flat while the bow of the latter is large indeed.Then, based on indications collected from simulations, we performed the bonding of a Si/Si homostructure in an EVG®ComBond® at 250°C. The same bonding conditions were used for an implanted germanium on silicon heterostructure. As shown in Figure 2, both bond pairs exhibited a bow close to that from FE simulations.After that, a splitting step was carried out, resulting in a thin germanium film on a silicon wafer (200mm), as shown in Figure 3. The film was transferred almost to the whole surface. The bow after splitting was of 10µm, a value not so far from the simulated value of 28.6 µm.As far as tensile stress was concerned, we used X-Ray Diffraction to gain access to the lattice parameter deformation and thus the tensile stress, 0.05% and 72 MPa, respectively (Figure 4). In comparison, FE simulation gives us 107 MPa of tensile stress after splitting. The main advantage of our approach is the lack of misfit dislocations in the Ge film, at variance with Ge epitaxy on Si (with a threading dislocations density typically around 107 cm-2, then).The presentation will focus, first, on the simulation tool and the manufacturing process used to fabricate such stressed germanium films. Then, stress calculus will be detailed. Finally, TEM imaging of cross-sections, XRD and bow measurements will help us better understand the specificities of such thin Ge films transferred on Si bulk wafers. Higurashi E. Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices. Jpn J Appl Phys. 1 avr 2018;57(4S):04FA02.King RR, Law DC, Edmondson KM, Fetzer CM, Kinsey GS, Yoon H, et al. 40% efficient metamorphic GaInP∕GaInAs∕Ge multijunction solar cells. Appl Phys Lett. 30 avr 2007;90(18):183516.Scappucci G, Kloeffel C, Zwanenburg FA, Loss D, Myronov M, Zhang JJ, et al. The germanium quantum information route. Nat Rev Mater. oct 2021;6(10):926-43.Abadie K, Fournel F, Morales C, Vignoud L, Colona JP, Widiez J. Manufacturing of Optimized Ge Substrates Using a Covalent Bonding Process. ECS Meet Abstr. 23 nov 2020;MA2020-02(22):1623.Takagi H, Kikuchi K, Maeda R, Chung TR, Suga T. Surface activated bonding of silicon wafers at room temperature. Appl Phys Lett. 15 avr 1996;68(16):2222-4.Rebhan B, Vanpaemel J, Dragoi V. 200 mm Ge Wafer Production for Oxide-Free Si-Ge Direct Wafer Bonding. ECS Trans. 8 sept 2020;98(4):87-100.Chao YL, Tong QY, Gösele UM. Thermomechanical stress in silicon on quartz wafer bonding and Smart Cut® process. MRS Proc. 2001;681:I5.10. [1] Trademark from S.O.I.T.E.C. .S.A. Figure 1

GaAs to Si Direct Wafer Bonding at T ≤ 220 °C in Ambient Air Via Nano-Bonding™ and Surface Energy Engineering (SEE)

When different semiconductors are integrated into hetero-junctions, native oxides generate interfacial defects and cause electronic recombination. Two state-of-the-art integration methods, hetero-epitaxy and Direct Wafer Bonding (DWB), require temperatures, T > 400 °C to reduce native oxides. However, T > 400 °C leads to defects due to lattice and thermal expansion mismatches. In this work, DWB temperatures are lowered via Nano-Bonding™ (NB) at T ≤ 220 °C and P ≤ 60 kPa (9 psi). NB uses Surface Energy Engineering (SEE) at 300 K to modify surface energies (γT) to far-from-equilibrium states, so cross-bonding occurs with little thermal activation and compression. SEE modifies γT and hydro-affinity (HA) via chemical etching, planarization, and termination that are optimized to yield 2-D Precursor Phases (2D-PP) metastable in ambient air and highly planar at the nano- and micro- scales. Complementary 2D-PPs nano-contact via carrier exchange from donor 2D-PP surfaces to acceptor ones. Here, NB models and SEE are applied to the DWB of GaAs to Si for photovoltaics. SEE modifies (1) the initial γT0 and HA0 measured via Three Liquid Contact Angle Analysis, (2) the oxygen coverage measured via High Resolution Ion Beam Analysis, and (3) the oxidation states measured via X-Ray Photoelectron Spectroscopy. SEE etches hydrophobic GaAs oxides with γT = 33.4 ± 1 mJ/m2, and terminates GaAs (100) with H+, rendering GaAs hydrophilic with γT = 60 ± 2 mJ/m2. Similarly, hydrophilic Si native oxides are etched into hydrophobic SiO4H2. H+- GaAs nano-bonds reproducibly to Si, as measured via Surface Acoustic Wave Microscopy, validating the NB model and SEE design.

Effect of Combined Hydrophilic Activation on Interface Characteristics of Si/Si Wafer Direct Bonding

Wafer direct bonding is an attractive approach to manufacture future micro-electro-mechanical system (MEMS) and microelectronic and optoelectronic devices. In this paper, a combined hydrophilic activated Si/Si wafer direct bonding process based on wet chemical activation and O2 plasma activation is explored. Additionally, the effect on bonding interface characteristics is comprehensively investigated. The mechanism is proposed to better understand the nature of hydrophilic bonding. The water molecule management is controlled by O2 plasma activation process. According to the contact angle measurement and FTIR spectrum analysis, it can be concluded that water molecules play an important role in the type and density of chemical bonds at the bonding interface, which influence both bonding strength and voids’ characteristics. When annealed at 350 °C, a high bonding strength of more than 18.58 MPa is obtained by tensile pulling test. Cross sectional SEM and TEM images show a defect-free and tightly bonded interface with an amorphous SiOx layer of 3.58 nm. This amorphous SiOx layer will induce an additional energy state, resulting in a lager resistance. These results can facilitate a better understanding of low-temperature hydrophilicity wafer direct bonding and provide possible guidance for achieving good performance of homogenous and heterogenous wafer direct bonding.

Heterogeneous Integration of III–V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

III-V materials, such as InGaAs and InP, are highly attractive for high-performance electronics and optoelectronics owning to their high carrier mobilities and potential for bandgap engineering. Integration on silicon substrates, however, is a key requirement to enable widespread adoption of these materials. In this work, direct wafer bonding (DWB) of III-V materials is explored as a low-temperature enabling technology for Si integration. For high-performance logic and RF electronics, DWB is compared to competing integration technologies and is shown to exhibit higher device performance due to its relatively low process complexity and thermal impact (~300 °C). Due to the low thermal impact of DWB, it is also uniquely suitable for 3-D integration, i.e., vertical stacking of multiple functional layers. III-V optoelectronics are attractive in such 3-D stacks, where they can enable high-efficiency tunable lasers together with Si photonics integrated circuits. DWB is here compared to selective epitaxy as an integration route for InP-on-Si microdisk lasers. Plasmonics are explored as well, allowing scaling of integrated III-V photonic devices beyond the diffraction limit of light. The results of this work show that DWB is a highly promising integration route for III-V materials for both electronics and optoelectronics applications.

A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

(Invited) Germanium-Tin Based Nano-Electronic and Photonic Devices

1. Introduction Germanium-Tin (Ge1-x Sn x ) alloy has many attractive properties that make it promising for many applications in nano-electronic and photonic devices and systems. GeSn has both higher hole and electron mobilities than Ge and Si to possibly enable scaling of the supply voltage for future high performance field-effect transistors (FETs). In addition, the tunable bandgap of GeSn by changing Sn compositions helps to extend the photo detection range beyond what can be achieved by Ge, covering wavelength larger than 1.55 µm.In this paper, we discuss the research and development of utilizing GeSn for various applications in nano-electronic and photonic devices. This includes multi-gate GeSn p-channel FETs (pFETs) on GeSn-on-insulator (GeSnOI) substrates, realization of ultra-low contact resistivity by incorporation Sn into Ge for the metal/GeSn S/D contact, and GeSn photodetectors for applications at 2 µm wavelength range. 2. GeSn pFinFETs with Sub-10 nm Fin Width on GeSnOI Substrates Large-area GeSnOI substrates were fabricated using direct wafer bonding (DWB) and layer transfer techniques at a 200 mm wafer scale [1]. This GeSnOI substrate, together with the multi-gate architecture, enabled the realization of high performance Ge1-x Sn x p-FETs with ultra-scaled channel length down to 50 nm [2]. An optimized try etch process was developed to fabricate GeSn FinFETs with fin width less than 10 nm. Excellent electrical characteristics were achieved with subthreshold swing of 63 mV/decade, intrinsic transconductance of 900 µS/µm at VDS of -0.5 V, and high-field effective mobility of 275 cm2/V·s. 3. Metal/ GeSn p-type Contact with Ultra-low Contact Resistivity. GeSn has a smaller hole Schottky barrier and a hole effective mass (mh ) as compared to Ge. These advantages make GeSn attractive for low-resistance p-type contacts. In-situ Ga doping was introduced during the epitaxial growth of GeSn using molecular-beam epitaxy (MBE) and more than 50% reduction of specific contact resistivity ρc has been observed by incorporation of 5% Sn into Ge [3]. Further optimization of GeSn doping process by surface segregation or cold implantation reduces ρc of Ti/p+-GeSn to sub-10-9 Ω-cm2 regime [4]. The ultra-low ρc of Ti/p+-GeSn is retained after anneal at 420 oC for 1 hour, showing adequate thermal stability for BEOL process in current CMOS technology [5]. 4. GeSn Photo-detectors for Applications at 2 µm Wavelength Range High-speed photo detection was demonstrated beyond traditional telecommunication bands and reaching at 2 μm band, realized by GeSn/Ge multiple-quantum-well (MQW) photodiode on Si substrate [6]. GeSn/Ge MQW structure was employed to increase the critical thickness (hc ) of epitaxial GeSn on Ge virtual substrate. A decent responsivity of 15 mA/W was obtained at 2 μm. A low leakage current density of 44 mA/cm2 was achieved at reverse bias of 1 V, which is among the lowest reported values for all GeSn photodiodes. A 3-dB bandwidth (f 3-dB) larger than 10 GHz was experimentally demonstrated directly at 2 μm. Acknowledgment We would like to acknowledge the funding support from Singapore Ministry of Education Tier 2 grants (R-MOE2018-T2-1-137 and MOE2018-T2-2-154).[1] D. Lei et al., Appl. Phys. Lett., 109, 022106, 2016.[2] D. Lei et al., VLSI Symposia, 2018, 197-198.[3] Y. Wu et al., J. Appl. Phys., 122, 224503, 2017.[4] Y. Wu et al., VLSI Symposia, 2018, 77-78.[5] Y. Wu et al., IEEE Electron Device Lett., 40, 1575-1578, 2019.[6] S. Xu et al., IEDM, 2018, 544-547.

Direct Semiconductor Wafer Bonding in Non-Cleanroom Environment: Understanding the Environmental Influences on Bonding

We investigated semiconductor direct wafer bonding in a regular, non-cleanroom environment to understand environmental influences on bonding characteristics. The correlations among surface treatments, particle densities, bonding strengths, and interfacial conductivities were systematically investigated. On the basis of our investigation and condition optimization, we realized direct semiconductor bonding in the regular atmosphere with high interfacial mechanical stabilities and electrical conductivities, sufficient for device applications. Furthermore, we demonstrated fabrication and operation of solar cells using the developed bonding technique, with current paths across the bonded interfaces. These results and related technical insights may be useful for a low-cost, simpler manufacture of high-performance electrical and optical devices.

InGaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

InGaSb-on-insulator (InGaSb-OI) and InAs/InGaAs/InAs-on-insulator (InAs/InGaAs-OI) structures have been realized on Si by a direct wafer bonding (DWB) technology using atomic-layer-deposition Al2O3. While strain introduced in InGaSb channel layers grown on InAs can enhance the hole mobility of the Sb-based channel layers, a difficult issue of fabricating InGaSb-OI wafers is to obtain a smooth InGaSb surface, which is mandatory for wafer bonding. In this study, the surface of a 20-nm-thick In0.185Ga0.815Sb channel grown on an InAs (100) substrate and an InAs (2.5 nm)/In0.185Ga0.815Sb (20 nm)/InAs (2.5 nm) channel with a 20-nm-thick GaSb buffer layer grown on an InAs (100) substrate by metal-organic chemical vapor deposition have a root mean square of the surface roughness as low as 0.16 and 0.22 nm, respectively, over a scan area of 10 × 10 μm2, which are smooth enough to employ the wafer bonding. As a result, the fabrication of the InGaSb-OI wafers by the DWB and the operation of InGaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) by using the DWB wafers are demonstrated. Also, the performance of InGaSb-OI p-MOSFETs is found to be improved by inserting ultrathin InAs layers between InGaSb and insulating buried oxide layers. An InGaSb-OI and an InAs/InGaAs-OI p-MOSFET under the accumulation-mode operation exhibit a peak mobility of ∼161 and ∼273 cm2/V s, respectively. The channel hole mobility of the InGaSb-OI p-MOSFET is higher than that of the GaSb-on-insulator (GaSb-OI) p-MOSFET and can exceed that of Si p-MOSFETs.

Large area stress free Si layer transfer onto Corning glass substrate using ion-cut

We report on the large area stress free single crystal silicon (Si) layer transfer onto glass substrate using hydrogen ion (H+) implantation and heterogeneous direct wafer bonding (DWB) (ion-cut process). Si wafers were implanted with H+ ions at room temperature followed by the DWB between the Si wafer and glass substrate. Post-implantation annealing studies were performed at different temperatures. The root mean square surface roughness of the H-implanted Si wafer and glass substrate was measured to be 0.3 nm and 0.5 nm, respectively. At an annealing temperature of 330 °C, a thin layer of the Si wafer was transferred onto the glass substrate. The average thickness of the transferred layer was found to be ∼605 nm with surface roughness of 4 nm. Raman spectroscopy confirmed that the transferred Si layer was stress free and retained its crystallinity. Large area transfer of high quality stress free Si-on-glass substrate is demonstrated using heterogeneous DWB and ion-cut process.

The Role of Misorientation in Direct Wafer Bonded III-V Materials

Direct wafer-bonding is a promising approach to materials integration for heterojunction structures not realizable through epitaxial means. Without lattice-parameter mismatch restrictions, wafer-bonding opens up a myriad of possibilities of materials combinations for many novel electronic device structures. In fact, wafer-bonding of III-V semiconductor materials was used to fabricate high-efficiency multijunction solar cells [1,2]. In this work, the effect of misorientation (both relative tilt and rotation) on the electronic properties across the bonded interface was studied by fabricating GaAs and InP homojunction and heterojunctions. To study the role of relative tilt, (001) n-type GaAs and (001) n-type InP wafers with offcut angles of 4° towards <111>A and nominal on-axis substrates were bonded to form relative tilts of 0°, 4°, and 8°. Current-voltage (I-V) curves were measured at various temperatures ranging from 90 K to 340 K to determine the interfacial barrier heights using the Seager and Pike electron model [3]. Then, to study the effect of rotation, (001) n-type InP wafers with twist angles ranging from 0° to 90° in 15° increments were bonded. Prior to bonding, the wafers were first cleaved into quarters and submerged in an NH4OH solution to remove the native surface oxide and then submerged in a 20% aqueous (NH4)2S solution for 5 minutes. After drying the wafers with N2, the wafers were brought face-to-face and very low pressure (kPa) was applied manually at room temperature and in ambient air pressure. The relative rotational misalignment was induced by rotating the top wafer prior to applying pressure. The wafers were then annealed at 400 °C for 2 hours to strengthen the bonded interface. Metal Ohmic contacts were deposited on each semiconductor surface and samples were diced into ~2 x 2 mm squares. We find that higher relative tilt across the interface leads to larger barrier heights. For example, in the GaAs/GaAs system the barrier height increased from 0.56 eV to 1.00 eV when increasing the tilt from 0° to 8°, respectively. Additionally, systems with at least one side InP (whether in an InP homojunction or InP/GaAs heterojunction) corresponded to lower barrier heights than the GaAs homojunction system. Regarding rotation, there is a discrepancy in literature on the effect of rotational misalignment. Kish et al. [4] claimed rotationally misaligning (001) III-V wafers by 20° and 90° result in the same decrease in electrical conductivity across the bonded interface compared to their 0° bonded wafers. However, Okuno et al. [5, 6] found that 0° and 90° bonded samples result in nearly equal electrical performance. Our findings show that the lowest interfacial resistance corresponded to misorientations of 0° and 90° while the greatest resistance corresponded to 45°, which was 30% higher than the lowest interfacial resistance. We conclude that the effect of rotational misalignment on the electrical conduction across bonded interfaces follows a sinusoidal pattern and its periodic effect on interfacial conductivity depends on the lattice symmetry of the wafer’s surface orientation, which has implications for bonding wafers with different surface symmetry. Electrical characterization of the interface enables us to understand the key factors that influence the properties of a bonded interface. We concluded that surface passivation, materials choice, and relative misorientation of the bonded materials are the determining factors that control the electrical performance of the bonded structure.

Direct Wafer Bonding of GaN for Power Devices Applications

Gallium nitride is a semiconductor material with a high potential for diverse applications as optoelectronic devices (high brightness LEDs, lasers, displays), wireless communication (microwave amplifiers, RF filters), high power and high temperature electronics, power devices or space applications requiring radiation-hard components working over wide temperature range. The economical advantages of GaN-based applications imposed the development of new manufacturing technologies. Wafer bonding was already adopted by semiconductor industry for consumer electronics, automotive or space applications so existing process solutions could be further developed for the new applications. One of the most significant benefits of using wafer bonding for GaN-based applications is the possibility to combine GaN with various substrate materials offering a high flexibility by imposing strict quality requirements only to the surfaces to be joined together by bonding and not to their crystal structure. The diversity of the new devices imposes different design criteria for the wafer bonding process. In order to provide a good platform for manufacturing the European research project AGATE aimed to create a substrate manufacturing pilot line to provide high quality substrates to device manufacturers. As main target, high quality substrates were produced by transferring GaN layers to different engineered substrates by a wafer bonding and layer transfer process. The process flow was: - The GaN layers on Sapphire substrates were coated with silicon dioxide layers and planarized by CMP - The Molibdenum substrates/ Poly-AlN substrates were coated with silicon dioxide layers and planarized by CMP - Both wafers were plasma activated using nitrogen plasma - The wafers were bonded at room temperature and further thermally annealed at low temperatures - The Sapphire substrate was removed. In order to further expand the application field of the pilot line the oxide-free direct bonding of GaN on Si was performed. In this approach, the process flow used was as below: - The GaN layers on Sapphire substrates were surface activated using ion beam sputtering for removing native oxides and contaminants from the surface. - The Si wafers were surface activated using same principle and native oxide was removed. - The GaN-Si direct bonding was performed in situ under high vacuum at room temperature, then thermal annealing was performed at low temperature. This work presents experimental details on the two process flows described. The incoming substrates were inspected by measuring the surface microroughness by Atomic Force Microscopy (AFM), their geometry (bow measurement using white light interferometry) and the presence of oxides on their surfaces was investigated by elipsometry. The bonded substrates were characterized in terms of bow and the bonding quality was inspected using visual inspection and Scanning Acoustic Microscopy (SAM). The oxide free bonds were characterized by cross-section TEM and EDAX and their thermal and electrical performance were measured. Figure 1

Direct Wafer Bonding of GaN for Power Devices Applications

Over the past decade the interest in gallium nitride – based electronic applications increased significantly. The economical advantages of GaN-based applications imposed the development of new manufacturing technologies. Among them, wafer bonding process solutions could be further developed and optimized for the manufacturing of GaN engineered substrates. The most significant benefit of using wafer bonding for GaN-based applications is the possibility to combine GaN with various substrate materials, offering a high flexibility by imposing strict quality requirements only to the surfaces of the substrates and not to their crystal structure.This work proposes two different process flows for “GaN-on-Something” substrates manufacturing. The features and benefits of the two process flows are illustrated by experimental results.

Strain relaxation of germanium-tin (GeSn) fins

Strain relaxation of biaxially strained Ge1-xSnx layer when it is patterned into Ge1-xSnx fin structures is studied. Ge1-xSnx-on-insulator (GeSnOI) substrate was realized using a direct wafer bonding (DWB) technique and Ge1-xSnx fin structures were formed by electron beam lithography (EBL) patterning and dry etching. The strain in the Ge1-xSnx fins having fin widths (WFin) ranging from 1 μm down to 80 nm was characterized using micro-Raman spectroscopy. Raman measurements show that the strain relaxation increases with decreasing WFin. Finite element (FE) simulation shows that the strain component in the transverse direction relaxes with decreasing WFin, while the strain component along the fin direction remains unchanged. For various Ge1-xSnx fin widths, transverse strain relaxation was further extracted using micro-Raman spectroscopy, which is consistent with the simulation results.

Fabrication of InGaAs-on-Insulator Substrates Using Direct Wafer-Bonding and Epitaxial Lift-Off Techniques

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO.

Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding.

This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs) by wafer direct bonding, which utilizes both the wet chemical and O2 plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC) substrates.

A Comparative Study: Void Formation in Silicon Wafer Direct Bonding by Oxygen Plasma Activation with and without Fluorine

A quantitative evaluation of void formation in plasma activated bonding of 200-mm silicon wafers is demonstrated. As a comparison, the wafers were treated with oxygen plasma or fluorine containing oxygen plasma prior to bonding, respectively. The bonding was performed at the room temperature (∼25°C), and all the bonded pairs were annealed from 200 to 800°C. Results shows adding a small amount of fluorine into the oxygen plasma could decrease the hydrophilicity of the silicon surfaces, and effectively mitigate void formation at the bonding interfaces during the subsequent annealing process. Moreover, long plasma treatments (e.g. >60 s) may produce more porous surfaces resulting in more annealing voids. A short fluorine containing plasma treatment (e.g. ∼10 s) is able to remove organic contaminants efficiently and causes restricted hydrophilic surfaces with less subsurface damages. It may lead to much fewer voids at bonding interfaces during the annealing. Void formation models are proposed to gain insight the mechanism of the plasma activated bonding without and with fluorine, respectively.