Wafer-bonding Process Research Articles

(Invited) Al-Al Waferbonding Process Development for Heterogeneous Integration

3D heterogeneous integration provides the possibility to combine dissimilar semiconductor technologies and add new components to obtain a higher performance and increase the functionality. Aligned Wafer level bonding, where the chips are vertically interconnected is known as one of the key technologies needed for 3D integration. Here, Aluminum to aluminum bonding is very attractive due to its easy compatibility to complementary metal-oxide-semiconductor (CMOS) processes. Furthermore Al-Al bonding provides not only the mechanical attachment between different wafers but also enables a good electrical and thermal conductivity. One of the main challenges for Al-Al thermocompression bonding is the formation of aluminum oxide which inhibits uniform and reliable Al-Al bonding at low temperatures with minimum bond forces. To overcome this limitation, this work presents a surface activated bonding process carried out in an EVG® ComBond® 200 mm automated high vacuum wafer bonding system. Here, the surface oxide is first removed with an argon plasma treatment. Without breaking vacuum to avoid a reoxidation, the wafers are optically aligned to each other and then bonded by applying force and temperature.This paper shows an integration concept for patterned 200 mm Al-Al bonded wafers and focusses on different factors influencing the quality of the Al-Al bonding. The bond quality is evaluated with various characterization methods. For electrical characterization single contacts with sizes down to 10 µm x 10 µm are analyzed. To characterize the bond interface C-mode scanning acoustic microscopy (C-SAM), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) are used. To calculate the bond strength, shear force measurements are carried out. The alignment accuracy is evaluated with an infrared microscope measuring the overlay of specific alignment marks at different dice across the wafer.A great factor influencing the bonding quality are the process parameters during the actual bonding process. Here, we vary the duration of the argon plasma activation from 1.5 to 5 min. Additionally, the impact of the bonding temperature in the range of 200 to 300 °C and the influence of the bonding force between 20 and 60 kN is investigated. Furthermore the bonding time is varied from 15 to 60 min. The best results with contact resistances in the mΩ-Range and a bonding yield >95% are achieved for wafers bonded for 1 h at 300 °C with 60 kN and an activation time of 5 min.Besides the bonding parameters, also the wafer fabrication prior to the bonding process has a significant influence on the Al-Al bond quality. In this context, the local and global topography of the wafers play an important role. An improved wafer flatness increases the contact area during bonding and can thus contribute to a better bonding result. In order to reduce the surface roughness of the Al bonding pads, we vary the parameters for the aluminum deposition and analyze the impact of different adhesion/barrier layers below the aluminum bonding film. The paper shows that also the tungsten plugs under the Al bonding pads affect their topography and thus the bond quality. In addition, we modify an etch-mask influencing the condition of the Al bonding pads and directly correlate it to the bonding yield and electrical resistance. Moreover, the impact of the wafer bow on the bond strength is studied.Even the processes that follow the Al-Al bonding can still negatively affect the final result. After bonding a backside grinding process is used, which causes silicon dust on the wafer surface and requires an additional cleaning step. This study shows the effect of an ultrasonic clean on the measured bond strength.In summary we present a surface activated, low temperature Al-Al bonding process of patterned 200 mm wafers with a high bonding yield, low contact resistances and an alignment accuracy close to 1 µm. Our work presents an integration concept for Al-Al bonded wafers and highlights different factors that influence the bonding result.

(Invited) Al-Al Waferbonding Process Development for Heterogeneous Integration

This paper presents a surface-activated Al-Al wafer bonding process for patterned 200 mm wafers that removes the native oxide in an argon plasma and enables high bond quality with accurate alignment at temperatures below 300 °C. The study focuses on various factors that influence the final Al-Al bond in terms of contact resistance and shear strength. In addition to temperature, force and time during the actual bonding process, these include steps during the wafer fabrication that affect the Al bonding pads and the wafer bow. Furthermore, the impact of a post-bond cleaning process on the final bond result is analyzed. This work shows a low temperature Al-Al bonding process with high yield >90%, excellent bond strength >150 MPa and contact resistances in the mΩ range.

(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology

This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon.

Study on P-AlGaAs/Al/Au Ohmic Contact Characteristics for Improving Optoelectronic Response of Infrared Light-Emitting Device.

The Al/Au alloy was investigated to improve the ohmic characteristic and light efficiency of reflective infrared light-emitting diodes (IR-LEDs). The Al/Au alloy, which was fabricated by combining 10% aluminum and 90% gold, led to considerably improved conductivity on the top layer of p-AlGaAs of the reflective IR-LEDs. In the wafer bond process required for fabricating the reflective IR-LED, the Al/Au alloy, which has filled the hole patterns in Si3N4 film, was used for improving the reflectivity of the Ag reflector and was bonded directly to the top layer of p-AlGaAs on the epitaxial wafer. Based on current-voltage measurements, it was found that the Al/Au alloyed material has a distinct ohmic characteristic pertaining to the p-AlGaAs layer compared with those of the Au/Be alloy material. Therefore, the Al/Au alloy may constitute one of the favored approaches for overcoming the insulative reflective structures of reflective IR-LEDs. For a current density of 200 mA, a lower forward voltage (1.56 V) was observed from the wafer bond IR-LED chip made with the Al/Au alloy; this voltage was remarkably lower in value than that of the conventional chip made with the Au/Be metal (2.29 V). A higher output power (182 mW) was observed from the reflective IR-LEDs made with the Al/Au alloy, thus displaying an increase of 64% compared with those made with the Au/Be alloy (111 mW).

HRXRD and micro-CT multiscale investigation of stress and defects induced by a novel packaging design for MEMS sensors

Advanced methods such as high-resolution X-ray diffraction and X-ray micro CT allow highly precise determination of materials' residual stress, volume, and lattice defects. Their conjoint exploitation offers a powering tool to facilitate the industrial implementation of novelties in microfabrication. The wafer-level packaging represents a critical step of the MEMS microfabrication resulting in a hermetic, defect- and stress-free interface. For the first time, such critical parameters are investigated related to a novel wafer-bonding process, namely Impulse Current Bonding (ICB), and compared to the standard anodic bonding technology used for MEMS production. The ICB does not induce any relevant residual stress at the interface above the limit of 1 MPa, determined by the unrivaled strain detectability of HRXRD. The bonding interface is devoid of any defects, as defined by X-ray micro-CT studies.The ICB technology reduces the thermal budget of the packaging up to 85% compared to the anodic bonding, which outlines an outstanding step forward in reducing the energy footprint. The extension of ICB to other materials systems such as glass to ceramic or metals makes this technology a promising candidate for numerous applications, including the design of biocompatible devices for bio-implants.

Study on combined reflectors for improving efficiency of high power near-infrared emitters

In this study, a combined reflector was suggested to improve the efficiency of high-power near-infrared (NIR) emitters. The combined reflector was fabricated by combining a distributed Bragg reflector (DBR) and an omnidirectional reflector (ODR). In the wafer bond process required for fabricating a high-power NIR emitter, the combined reflector was fabricated such that the developed DBR, which grew as the lowest layer of the epitaxial structure, bonded directly to the ODR deposited on the silicon wafer. The DBR in the combined reflector efficiently reflected photons emitted downward at a certain angle of 20° from the active region. A large number of photons, except at a certain angle by the DBR, are reflected by the other ODR. Therefore, the combined reflector might have favorable reflectivity properties produced by either DBRs or ODRs. As a result, photons emitted downward from the active region of the near-infrared emitter could be efficiently reflected upward and sideways by using a combined reflector of DBRs and ODR. From the results of the characteristics, the NIR emitter with the efficient combined reflector displays a 166% and 118% higher output power than that with either DBRs or ODR. Further, it was re-proved that there exist paramount characteristics of DBRs and ODR in a combined reflector through measurement of photometric and radial theta.

Outperforming piezoelectric ultrasonics with high-reliability single-membrane CMUT array elements

It has long been hypothesized that capacitive micromachined ultrasound transducers (CMUTs) could potentially outperform piezoelectric technologies. However, challenges with dielectric charging, operational hysteresis, and transmit sensitivity have stood as obstacles to these performance outcomes. In this paper, we introduce key architectural features to enable high-reliability CMUTs with enhanced performance. Typically, a CMUT element in an array is designed with an ensemble of smaller membranes oscillating together to transmit or detect ultrasound waves. However, this approach can lead to unreliable behavior and suboptimal transmit performance if these smaller membranes oscillate out of phase or collapse at different voltages. In this work, we designed CMUT array elements composed of a single long rectangular membrane, with the aim of improving the output pressure and electromechanical efficiency. We compare the performance of three different modifications of this architecture: traditional contiguous dielectric, isolated isolation post (IIP), and insulated electrode-post (EP) CMUTs. EPs were designed to improve performance while also imparting robustness to charging and minimization of hysteresis. To fabricate these devices, a wafer-bonding process was developed with near-100% bonding yield. EP CMUT elements achieved electromechanical efficiency values as high as 0.95, higher than values reported with either piezoelectric transducers or previous CMUT architectures. Moreover, all investigated CMUT architectures exhibited transmit efficiency 2–3 times greater than published CMUT or piezoelectric transducer elements in the 1.5–2.0 MHz range. The EP and IIP CMUTs demonstrated considerable charging robustness, demonstrating minimal charging over 500,000 collapse-snap-back actuation cycles while also mitigating hysteresis. Our proposed approach offers significant promise for future ultrasonic applications.

Enhanced Light Output Power on Near-Infrared Light-Emitting Diodes with TITO/Ag Multilayer Reflector.

A titanium–indium tin oxide (TITO) multilayer reflector was investigated to improve the light efficiency of high-power, near-infrared, light-emitting diodes (NIR-LEDs). The TITO/Ag was fabricated by combining a patterned TITO and an omnidirectional reflector (ODR). For fabricating a high-power NIR-LED, the wafer bond process required the TITO reflective structure, which has patterns filled by AlAu contact metal, bonded directly to the Ag reflector deposited on the silicon wafer. Among Ag-based single- and multilayer reflectors, the TITO/Ag showed the highest reflectance (R = 96%), which was favorable for wafer-bonded high-power NIR-LEDs. Therefore, the TITO/Ag reflector enabled the production of wafer-bonded NIR-LED chips that exhibit superior output performance (190 mW) compared with conventional cases using a single Ag reflector.

A holistic X-ray analytical approach to support sensor design and fabrication: Strain and cracking analysis for wafer bonding processes

Devices such as sensors, actuators, or micro-electromechanical systems (MEMS) are obtained by a variety of microfabrication processes. Many of these processes influence the material systems by the introduction of strain and defects, which may affect the final device's performance and reliability. Indeed, controlling materials' status during the microfabrication is fundamental for the process optimization itself and for guaranteeing the highest devices performances during their lifetime. In this work, a conjoint analytical approach between high-resolution X-ray diffraction (HRXRD) and X-ray micro-computed tomography (CT) evaluates an innovative silicon-to-sapphire wafer bonding process. Large cracks 30–60 µm-thick were identified in both crystals by micro-CT and related to the interfacial high-stress release. In parallel, a multi-domain microstructure associated with strain and tilt affect the silicon crystallinity due to smaller cracks and defects which originate at the bonding interface and travel to the outer part of the crystal. The effectiveness of the bonding is also assessed by our approach and further enforced by means of SEM observation of the sample cross-section. Here, a unique approach by combining X-ray micro CT with HRXRD for a holistic evaluation of silicon-to-sapphire wafer-bonding processes and correlate the micrometer scale and volumetric defect detection (voids and cracks) with atomic-level strain and defect analysis is presented.

Determination of stress, cracks and defects density in crystals after wafer-bonding processes: a novel HRXRD–X-ray micro-CT conjoint analytical approach

Determination of stress, cracks and defects density in crystals after wafer-bonding processes: a novel HRXRD–X-ray micro-CT conjoint analytical approach

Surface Acoustic Wave Devices Using Lithium Niobate on Silicon Carbide

This work demonstrates a group of shear horizontal (SH0) mode resonators and filters using lithium niobate (LiNbO3) thin films on silicon carbide (SiC). The single-crystalline X-cut LiNbO3 thin films on 4H-SiC substrates have been prepared by ion-slicing and wafer-bonding processes. The fabricated resonator has demonstrated a large effective electromechanical coupling (k 2 ) of 26.9% and a high-quality factor (BodeQ) of 1228, hence resulting in a high figure of merit (FoM = k 2 · BodeQ) of 330 at 2.28 GHz. Additionally, these fabricated resonators show scalable resonances from 1.61 to 3.05 GHz and impedance ratios between 53.2 and 74.7 dB. Filters based on demonstrated resonators have been demonstrated at 2.16 and 2.29 GHz with sharp roll-off and spurious-free responses over a wide frequency range. The filter with a center frequency of 2.29 GHz shows a 3-dB fractional bandwidth of 9.9%, an insertion loss of 1.38 dB, an out-of-band rejection of 41.6 dB, and a footprint of 0.75 mm 2 . Besides, the fabricated filters also show a temperature coefficient of frequency of -48.2 ppm/°C and power handling of 25 dBm. Although the power handling is limited by arc discharge and migration-induced damage of the interdigital electrodes and some ripples in insertion loss and group delay responses are still present due to the transverse spurious modes, the demonstrations still show that acoustic devices on the LiNbO3-on-SiC platform have great potential for radio-frequency applications.

Reactive wafer bonding with nanoscale Ag/Cu multilayers

Reactive bonding using nanoscale multilayers based on the high specific surface/interface energy is a promising low-temperature and low-pressure wafer-bonding process. Herein, Si wafers were bonded using nanoscale Ag/Cu multilayers in N2 or the ambient atmosphere. A flawless joint composed of Ag-rich and Cu-rich face-centered cubic (fcc) phases was achieved in N2 with 22.2 MPa shear strength. However, a peculiar “fcc-(Ag)+voids/Cu2O/fcc-(Ag)+voids” three-layer sandwich structure with 11.1 MPa shear strength was formed due to significant out segregation of Cu toward the bonding-interface in the ambient atmosphere. The bonding mechanism and the role of oxygen were unveiled based on CALPHAD (CALculation-of-PHAse-Diagram) thermodynamic modeling.

A Low-Temperature Nickel Silicide Process for Wafer Bonding and High-Density Interconnects

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal-silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion.

Epitaxial Oxides on Glass: A Platform for Integrated Oxide Devices

The fabrication of epitaxial, ultra-thin SrTiO3 (STO) on thick SiO2 without the need for complicated wafer-bonding processes has been demonstrated. The resulting transition metal oxide (TMO)-on-glass layer stack is analogous to traditional silicon-on-insulator (SOI) wafers, where the crystalline device silicon layer of SOI has been replaced by a crystalline functional TMO layer. Fabrication starts with ultra-thin body SOI on which crystalline STO is grown epitaxially by molecular beam epitaxy. The device silicon layer is subsequently fully oxidized by ex situ high-temperature dry O2 annealing, as confirmed by X-ray photoelectron spectroscopy, X-ray reflectivity, and high-resolution electron microscopy. STO maintains its epitaxial registry to the carrier silicon substrate after annealing and no evidence for degradation of the STO crystalline quality as a result of the TMO-on-glass fabrication process is observed. The ease of fabricating the TMO-on-glass platform without the need for wafer bonding will enab...

GaN LED on Quartz Substrate through Wafer Bonding and Layer Transfer Processes

A method to transfer GaN LED layers (which was grown initially on a Si substrate) to a quartz substrate is proposed and demonstrated. Quartz substrate is chosen due to its optical transparency to enhance the light extraction efficiency. The GaN LED-on-Si substrate was temporarily supported on a Si handle wafer. A quartz substrate was then bonded to the GaN LED layers-containing handle wafer. Finally, the handle wafer was released to realize the GaN LED layers on the quartz substrate. All substrates used were 200 mm in diameter. The transferred film demonstrates excellent optical properties. The GaN LED devices were then fabricated on coupon size samples (singulated from the 200 mm GaN LED on quartz substrate) using standard photolithography techniques. The mesas were formed by dry etching processes. The performance of the devices is promising and the details will be presented. Through this method, we can improve the light extraction efficiency and hence, benefit to the integration of Si-CMOS + LED platform for applications such as multi-color microdisplay.

GaN LED on Quartz Substrate through Wafer Bonding and Layer Transfer Processes

A method to transfer GaN LED layers (which were grown initially on a Si substrate) to a quartz substrate is proposed and demonstrated. Quartz substrate is chosen due to its optical transparency to enhance the light extraction efficiency. The GaN LED-on-Si substrate was temporarily supported on a Si handle wafer. A quartz substrate was then bonded to the GaN LED layers-containing handle wafer. Finally, the handle wafer was released to realize the GaN LED layers on the quartz substrate. All substrates used were 200 mm in diameter. The transferred film demonstrates excellent optical properties. The GaN LED devices were then fabricated on coupon size samples using standard photolithography techniques and dry etching processes. Through this method, we can improve the light extraction efficiency and hence, benefitial to the integration of Si-CMOS + LED platform for applications such as multi-color microdisplay.

Local tentative bonding method to maintain alignment accuracy in bonding process using resin as an adhesive material

The authors proposed a novel method to maintain the alignment accuracy in the wafer-bonding process, which uses a resin as an adhesive material. Recently, the resin has received attention as an adhesive material for wafer bonding in microelectromechanical system device fabrication because of its multiple advantageous material properties. However, because of its inherent material viscosity, the alignment accuracy cannot be easily maintained, particularly when two wafers are bonded with a thick resin after alignment. To solve this problem, they proposed a local tentative bonding method. After aligning the two wafers, they irradiated the adhesive resin layer between the wafers using a near-infrared (NIR) spotlight (wavelength = 1020 nm), which is transparent to Si wafers. Using several NIR irradiation spots aimed at the resin layer after aligning the wafers, the resin layer was bonded locally and tentatively, which was sufficiently secure to avoid wafer shifting in the subsequent process. The local tentative bonded areas acted as anchors, which held the wafers during the bonding process. They performed experiments to demonstrate the effectiveness of their method using resins, such as polyimide, benzocyclobutene and SU-8. Consequently, they achieved an alignment accuracy <5 µm, which is a significant improvement compared with the typical bonding results.

Practical CMUT Fabrication With a Nitride-to-Oxide-Based Wafer Bonding Process

The introduction of wafer-bonding technique to capacitive micromachined ultrasonic transducer (CMUT) fabrication offered advantages over the surface micromachining technique, such as simplified fabrication, better membrane uniformity, and increased active area. The conventional wafer-bonding CMUT process employs silicon-on-insulator (SOI) wafers to produce the vibrating membrane layer. However, the use of SOI wafers can lead to poor membrane thickness uniformity despite the high cost. Furthermore, an additional local-oxidation (LOCOS) process should be used for SOI-based wafer bonding process to improve breakdown voltage and reduce parasitic capacitance. This paper reports a nitride-to-oxide bonding process for CMUT fabrication, designed to achieve similar results as the LOCOS-added process reported by Park et al. , but without the need for SOIs and fabrication complexity. A fully functional CMUT designed for collapse-mode operation was fabricated and an immersion center frequency was measured to be 4.2 MHz with a 90% bandwidth. [2016-0210]

Fabrication of capacitive micromachined ultrasonic transducers with low-temperature direct wafer-Bonding technology

In this paper, the low temperature direct wafer-bonding technique under 350°C is used to fabricate the capacitive micromachined ultrasonic transducers (CMUTs) and the first illustration of CMUTs with a 15×15 array is obtained. In comparison with other wafer-bonding technology under high temperature beyond 400°C, the thermal stress and thermal deformation of CMUTs produced in the wafer-bonding process can be decreased largely because of low bonding temperature. What's more, the low temperature direct wafer-bonding technique is beneficial to combine the CMUTs chip with integrated circuits (ICs) as well as reduce the parasitic capacitance. Based on the low temperature direct wafer-bonding process, a silicon-on-insulator (SOI) wafer with the silicon device layer used for transducer membrane and a low-resistivity silicon substrate with the structured SiO2 layer are bonded to fabricate the main structure of CMUTs. Therefore, the parasitic capacitance of CMUTs can be further reduced since there is no metal auxiliary layer existing during the bonding process. The structure morphology and electrical characterization of fabricated CMUTs are tested in this paper. Then, the impedance-frequency curve and the corresponding phase-frequency curve of the CMUTs are obtained perfectly, which demonstrate that the fabricated CMUTs based on the low-temperature direct wafer-bonding technique present the fine mechanical and electrical characteristics.

Stress control of reactively sputtered thick NbN film on Si wafer changing the location of the substrate Si wafer against the Nb target on a magnetron cathode

We have been developing a superconducting NbN thin film coil in a spiral trench on a Si-wafer using MEMS technology. Connecting the coils on the different wafers using waferbonding process, a cylindrical wafer stack is to be formed as a unit of a compact SMES. The critical current density of our NbN film was measured to be around 1100 A/mm2. We measured critical current Ic of 47 mA for the previously fabricated coil of the film thickness tf = 0.5 μm. Ic in the spiral coil increases with tf. However, if we make the NbN film thicker, the film is apt to have higher lateral force caused by tensile or compressive stress which can cause peeling of the film from the Si substrate. It is well known that the stress of the sputtered thin films can be controlled from tensile to compressive stress by controlling the bombardment of high energy particles including argon atoms backscattered from the target surface. Based on this knowledge, a specially designed sputter-deposition apparatus was fabricated in which the substrate can be located not only at the different target-to-substrate distances but also at several different lateral distances from the central axis of the target (off-axis lateral shift). Using this apparatus, various stress conditions could be realized which contributed to fabrication of thick NbN film spiral coil in the trench. The film stress was calculated from bending analysis of the substrate Si wafer by stylus method using Stoney’s formula. The maximum compressive stress of 2.5 GPa was measured. By an off-axis lateral shift, tf could be increased from 0.5 to 1 μm. By increasing sputtering gas pressure from 0.7 to 2 Pa, the compressive stress could be mitigated and tf could be further increased from 1.0 to 3 μm. Up to now, we measured Ic of 220 mA for a NbN spiral coil at tf around 3 μm. More detailed adjustment of the deposition condition will bring further increase in tf, and hence Ic into sight.