WCDMA Mode Research Articles

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

ABSTRACTThe design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.

A 64-fJ/Conv.-Step Continuous-Time <formula formulatype="inline"> <tex Notation="TeX">$\Sigma \Delta$</tex></formula> Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital <formula formulatype="inline"> <tex Notation="TeX">$\Delta \Sigma$</tex></formula> Truncator

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.

A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

A low-power, multimode polar transmitter based on a two-point injection PLL with a linearized VCO is implemented in 65-nm CMOS technology. A wideband feedback loop, nested inside the PLL with negligible area and power consumption overhead, linearizes and accurately controls the tuning characteristic of the VCO, which is a key requirement when directly modulating the oscillator. Differential delay between AM-PM paths is predictable and is self-calibrated. In WCDMA mode, the transmitter achieves 42/-58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive band noise, and 2.9% EVM at 0-dBm output power while drawing 40-mA from a 3.6-V battery. The DG09 battery current is 25-mA based on a typical PA gain profile and the chip active area is 0.7-mm2.

Compact 1.5GHz to 2.5GHz multi-band multi-mode power amplifier

This paper presents a compact multi-band/multi-mode power amplifier (PA) for mobile terminals. The PA is reconfigurable within the size of 6.2 x 8.05mm2 and covers the frequency bands for mobile communications from 1.5GHz to 2.5GHz. The experimental results in terms of gain, output power, and adjacent channel leakage ratio are very close to those of actually-used single-band PAs in mobile terminals. To the best of our knowledge, this is the first time that a compact PA is presented that is less than 50mm2 and covers the 1.5, 1.7, 1.8, 1.9, 2.3, and 2.5-GHz bands for GSM, W-CDMA, and LTE modes.

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm/sup 2/ was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 /spl mu/V and 47 /spl mu/V in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V.