Voltage-mode Sense Amplifier Research Articles

Design and Performance Analysis of High-Performance Low Power Voltage Mode Sense Amplifier for Static RAM

In the prominent era of the digital world and Very Large-Scale Integration (VLSI) circuits, Static Random Access Memory (SRAM) provides a vital contribution to low-power and high-speed performance. Sense Amplifiers (SA) are a part of Complementary Metal-Oxide-Semiconductor (CMOS) memories used to read the stored information. This paper indicates a Dual-Voltage, Dual-Tail Level Restoration Voltage Latch Sense Amplifier (DVDTLR-VLSA). The design has been implemented using the LT SPICE tool at 180nm technology node with a 1.8V supply. Performance comparison of existing SA presented in literature with the proposed SA is examined based on different parameters like power, energy, delay, and current. The proposed design maintains power at 2.167uW that is decreased to half as against Dual Switch Transmission Gate Voltage SA (DTGVSA) and shows an appreciable depletion. Also, the current and delay results are improved. Dimensional analysis is also done for the proposed SA to examine the performance. After that, the effect of sleep transistors on the proposed SA examines the performance in comparison to delay and power parameters without sleep transistors. The DVDTLR-VLSA has minimal energy and power. Also, the delay is improved which may be determined more advisable for low-power operations.

Sense amplifier for ReRAM-based crossbar memory systems

ABSTRACT A voltage-mode sense amplifier circuit designed for resistive random-access memory (ReRAM)-based memory arrays is proposed. The sense amplifier is designed comprising of an inverting buffer so that it can operate at a very low voltage (150 mV), which is the typical READ output voltages of a ReRAM cell while the proposed differential comparator design utilises a reduced number of transistors (20%) compared with conventional design to determine the logic states of the ReRAM cell. A simulation with a 2 × 2 memory crossbar is performed and compared with existing voltage-mode and current-mode sense amplifiers and the proposed circuit shows better READ time (32% and 85%) and energy performance (54% and 59%) than existing methods.

Low Power Single Bit Cache Memory Architecture

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, static random access memory cell, and sense amplifiers such as voltage mode sense amplifier and a current-mode sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifiers and static random access memory cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte carlo simulation and process corner simulation also have been done. The conclusion arises that single bit cache memory architecture having volatge mode sense amplifier with forced stack technique over static random access memory in an architecture consumes the lowest power (9.108 µW) with an area of 6.613 × 30.48 mm2.

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM

In Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), the most commonly used timing scheme for conventional Voltage-mode Sense Amplifier (VSA) is the global activated timing. Obviously this method cannot obtain the optimal yield because different bit-cells have its sensing latency respectively. This paper proposes a self-timed voltage-mode sense scheme named ST-VSS which can enable optimal timing depending on the bit-cell discharging ability. Two circuit structures are proposed: The single SA structure uses a multiplexer at the input of the SA. Its successive sensing operations are implemented with input offset flipping. A dual SA structure is reconfigured by built-in-self-test (BIST) method to the opposite offset states to monitor sensing results from each other. The sensing operation can be immediately terminated after successful reading. The proposed ST-VSS is applied to a 32bits/word MRAM using 28-nm CMOS process. Simulation results show that the successful sensing rate across a wide range of voltages can be improved, comparing with the conventional scheme. The single SA structure obtains 32%~42% yield improvement, costs 44.1%/26.9%/19.3% energy, and brings 8.3%/5.8%/2.9% layout area penalty in 128/256/512 column depth, respectively. The dual SA structure gets 54%~65% yield improvement, costs 66.2%/38.6%/27.5% energy, and brings 26.4%/13.8%/7.1% area penalty in 128/256/512 column depth conditions, respectively.

Comparative Analysis of Leakage Reduction Techniques in Voltage Mode and Current Latch Sense Amplifiers in Sram Cell

In present paper, the comparative analysis of different type of low power reduction techniques has been performed by implementing in voltage mode and current latch sense amplifier 6-T SRAM cell. The low power reduction techniques have been realized in 6-T SRAM sense amplifiers using the 90-nm 1-V CMOS technologies. Total power dissipation of current latch sense amplifier is 14 μw which is 41.59 percent less than the voltage mode sense amplifier. It has been found that Sleep transistor technique is very effective to reduce leakage power as well as total power dissipation in voltage mode sense amplifier. However, this technique is not so efficient to reduce total power dissipation in current latch sense amplifier. Furthermore, it has been observed that Dual Sleep method is more effective to reduce total power dissipation in current latch sense amplifier.

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- ${\rm VDDmin}$ , and slow read access time ( $T _{\rm AC}$ ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current ( $I _{\rm DC-SET}$ ) resulting from the wide distribution of write (SET)-times ( $T _{\rm SET}$ ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately $1.8+{x}$ greater sensing margin for lower ${\rm VDDmin}$ and a $1.7+{x}$ faster read speed across a wide ${\rm VDD}$ range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the $I _{\rm DC-SET}$ of devices with a rapid $T _{\rm SET}$ . The SBWT scheme reduces ${\hbox{99}}+\%$ of the $I _{\rm DC-SET}$ with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved $T _{\rm AC} ={\hbox{404 ns}}$ when ${\rm VDD}={\hbox{0.27 V}}$ and confirmed the $I _{\rm DC-SET}$ cutoff by the SBWT.

A Review of Sense Amplifiers for Static Random Access Memory

Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs). This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM. Recent advances in developing SAs have paved the way for lower delay, lower energy, and higher reliability. For comparison, all SAs based on 65 nm CMOS technology are simulated under different power supplies, bit-line capacitances, and various process corners. When the bit-line capacitance is 50 fF, charge-transfer and current-mode SAs are about 40% faster than voltage-mode SAs, and the energy consumption of charge-transfer SA is 30% lower than that of other voltage-mode SAs. Delay and energy of HCI-trimming SA and multi-sized SA are about equal to that of voltage-mode SAs. Because of low bit-line precharged voltage, the energy of charge-limited sequential SA (CLSSA) is 64% lower than that of charge-transfer SA, while the delay of CLSSA is five times larger than the other SAs.

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

In advanced CMOS technologies where device mismatches are of major reliability concern, predicting the input-offset voltage of the sensing circuit is a crucial step in the design process as it has a direct impact on the yield. This work uses the Taylor expansion to derive a criterion to evaluate input-offset voltage of a latch-type voltage-mode sense amplifier. By innovatively setting the correct sensing criterion, this method provides a very simple, yet accurate and robust model to quantify the input-offset of the sense amplifier. The resulting offset expression incorporates three types of device mismatches, namely the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), the trans-conductance ( K = ¿C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0x</sub> W/L) and the capacitance (C). The model is then analyzed under the worst-case scenario. It is shown that V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> has the greatest influence on the offset voltage, followed by K and C mismatches. Second-order approximation is also considered when high-level mismatches are present. Extensive simulations have also been carried out to verify the accuracy of the model using three different CMOS technologies.