Voltage-mode Drivers Research Articles

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS

This paper presents a 4-wire, 3-level, and 16-Gb/s/wire transceiver array for short-reach interconnects. The proposed transceiver adopts the balanced single-ended signaling (BASES) to reduce the simultaneous switching noise (SSN) and the electro-magnetic interference (EMI). The four transmit encoders and voltage-mode drivers produce three-level, common-mode-balanced, and multi-lane signals. The receive terminations and equalizers utilize the CM-balancing property of the BASES coding to recover the transmitted signals with a high noise rejection capability. The 4-wire transceiver was fabricated in a 28-nm CMOS technology and achieved a 64-Gb/s aggregate data rate with 3.15-pJ/bit energy efficiency.

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter With 2-Tap FFE

This paper describes a voltage-mode transmitter that supports both non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) signal transmission. A 2-tap feed-forward equalizer (FFE) is implemented with PAM4 equalization logic consisting of three stages of logic gates and two separated voltage-mode drivers for multi-level generation. Equalization is performed in both the NRZ and PAM4 signal transmission modes. A prototype chip is fabricated using a 28-nm CMOS process. When transmitting 500-mVp-p signals using the proposed transmitter, 41.13 mW power is consumed from a 1-V power supply during the 32-Gb/s PAM4 transmission.

Single‐ended voltage‐mode duobinary transmitter with feedback time reduced parallel precoder

A duobinary transmitter (TX) is presented in a single-ended topology using voltage-mode drivers to support dynamic random access memory (DRAM) interface. A four-phase parallel duobinary precoder is included. It relaxes one of the critical timing requirements of the duobinary TX by reducing the feedback step of the precoder and performing its feedback at once. Fabricated in a 55 nm CMOS process, the TX occupies 0.053 mm2 active area. The TX achieves 10 Gbps operation at 6.8 pJ/b of energy efficiency and operates up to 12.8 Gbps at 7.6 pJ/b.

Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.

5 Gbit/s 2‐tap low‐swing voltage‐mode transmitter with least segmented voltage‐mode equalisation

A 2-tap low-swing voltage-mode transmitter which compensates the loss of channel at high frequency is proposed. The output driver of the proposed 2-tap transmitter consists of only two voltage-mode drivers, and thereby the design complexity of the pre-driver is greatly reduced compared with that of conventional 2 N -segmented voltage-mode drivers, where N is the number of equalisation control bits. The output impedance of each voltage-mode driver is adjusted not only to make the overall output impedance matched with the characteristic impedance of the channel, but also to achieve the desired equalisation coefficient by adopting the proposed calibration circuitry. With a high equalisation coefficient, the proposed output driver consumes less power compared with the hybrid voltage-mode driver with current-mode equalisation. The proposed transmitter is implemented using a 90 nm low-power CMOS process technology and achieves 0.79 pJ/bit without equalisation and 0.98 pJ/bit with 6 dB equalisation, at the data rate of 5 Gbit/s.

A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis

In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER=10 -12 ) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings

This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μ m CMOS. At ± 500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μ A ( 343 μ A for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.

A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS

Low-power (LP) high-speed serial I/O transmitters which include equalization to compensate for channel frequency-dependent loss are required to meet the aggressive link energy-efficiency targets of future systems. This brief presents an LP serial-link-transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in predriver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic-power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Fabricated in a 1.2-V 90-nm LP CMOS process, the transmitter supports an output swing range of 100–400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mV}_{{\rm ppd}}$</tex></formula> and up to 6 dB of equalization and includes output-duty-cycle control. The transmitter achieves 6-Gbit/s operation at 1.26-pJ/bit energy efficiency with 300- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mV}_{{\rm ppd}}$</tex></formula> output swing and 3.72-dB equalization.

Fully Digital Transmit Equalizer With Dynamic Impedance Modulation

This paper analyzes the energy efficiency of different transmit equalizer driver topologies. Dynamic impedance modulation is found to be the most energy-efficient mechanism for transmit pre-emphasis, when compared with impedance-maintaining current and voltage-mode drivers. The equalizing transmitter is implemented as a digital push-pull impedance-modulating (RM) driver with fully digital RAM-DAC back-end for pattern lookup. This back-end compensates for both duty-cycle distortion and driver nonlinearity, while providing a programmable pre-emphasis. A testchip fabricated in 90-nm CMOS process shows relatively small signal degradation from dynamic modulation of driver output impedance over a variety of 20 backplanes at 4 Gb/s, with energy efficiency of 2 pJ/bit at 100 mV of receiver eye. Despite this signal degradation, at the same performance point, the impedance modulating driver shows better energy efficiency than impedance-maintaining current and voltage-mode drivers.

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-㎛ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 ㎃ for a 400-㎷ output voltage swing.