Capacitor Voltage Imbalance Research Articles

Capacitor Voltage Balancing Control of MMC Sub-Module Based on Neural Network Prediction

The issue of sub-module (SM) capacitor voltage unbalance is a hot topic in the current research into the modular multilevel converter (MMC). An excellent strategy comprises mitigating the SM capacitor voltage imbalance by adjusting the SM on time. The traditional capacitor voltage balancing control regulates the speed to maintain accuracy. A unique SM capacitor voltage balancing control strategy is presented in this paper and is based on conventional capacitor voltage balance management and neural network prediction. Firstly, the SM capacitor voltage and arm current are speculated by operating the time series forecasting technique in real time, considering the dynamic changes in the SM capacitor voltage and arm current. Secondly, the SM capacitor voltage distinction between the actual and theoretical value is determined, and a deviation’s mixed Gaussian distribution is established to estimate its compensation voltage. Thirdly, the SM triggering sequence is anticipated by using the neural network along with the pilot values of the SM capacitor voltage, arm current, and the offset compensation value, and the control is executed. Finally, a three-phase, six-leg, eight-module, nine-level MMC model is built to verify the feasibility of the suggested approach.

Analysis and Mitigation of Transient Overvoltage and Voltage Imbalance in Submodule Capacitors for MMC-Based Grid Emulators

Analysis and Mitigation of Transient Overvoltage and Voltage Imbalance in Submodule Capacitors for MMC-Based Grid Emulators

A novel extendable multilevel inverter for efficient energy conversion with fewer power components: Configuration and experimental validation

SummaryMultilevel inverters (MLIs) are widely used in various sectors of power electronics. Some major benefits of using MLI are the high‐quality voltage output, harmonic reduction, and efficiency. However, MLIs also bear a range of disadvantages including an excessive number of components, high total standing voltage (TSV), and complicated control scheme. Thus, a novel cross‐switched neutral point clamped (CSNPC) nine‐level inverter is proposed. Many of the suggested MLIs use a large number of DC supplies and additional switches that are not fully utilized and generate high power loss. However, the proposed MLI topology has a smaller number of power electronic switches and DC supplies, leading to higher energy efficiency. Moreover, a simplified high frequency modulation technique, named hysteresis‐band‐based discontinuous pulse width modulation (DPWM) is devised to control the proposed MLI. This modulation scheme has effectively minimized capacitor voltage imbalance. Furthermore, the designed structure is extendable to a modular MLI, without any additional H‐bridge circuit. To verify its benefits over other recent similar types of MLIs, a thorough comparison is presented for the number of components and power losses. The proposed MLI has showed 95.54% efficiency, and the modular CSNPC can achieve a total harmonic distortion (THD) of 6.43%.

Modulation Methods for Balancing the Capacitor Voltages of N-Level Diode-Clamped Converters

Diode-clamped converters (DCCs) suffer from the inherent capacitor voltage imbalance problem. Most software-based voltage-balancing methods fall into the space-vector-modulation (SVM) category and the carrier-based pulse-width-modulation (CB-PWM) category. Despite their effectiveness for the three-level DCCs, it is not easy to extend them to a general <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -level topology. In this paper, a new modulation method of a category called good-switching (GS) PWM is proposed for balancing the capacitor voltages. The proposed method requires no parameter-tuning effort and is extremely simple to design even for the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -level topology regardless of the number of phases. It is also potentially applicable to other multilevel converters. The principle, the implementation, and the stability analysis of GS-PWM are elaborated for a generic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -level DCC. A modified GS-PWM scheme and an on-off control scheme are proposed to reduce the switching transitions for further realizing the advantages of the GS-PWM. Particularly, the on-off control can be extended to many other voltage-balancing methods. Simulation and experiments with a five-level DCC validate the proposed methods.

Mode analysis and fault-tolerant method of open-circuit fault for a three-level dual active bridge DC-DC converter

The three-level dual-active-bridge (TL-DAB) DC-DC converter is a promising dc-dc converter for high-voltage and high-power systems. Open-circuit faults on power switches are crucial issues for the TL-DAB dc-dc converters, resulting in various performance degradations such as dc bias and divided capacitor voltage imbalance. The mode analysis after fault is necessary for fault detection and fault-tolerant control. Subsequently, fault-tolerant control is essential to reduce or overcome these issues. In the proposed fault-tolerant method, when the primary side inner switch or the secondary side switch breaks down, the gate-driving signal of the complementary switch is recommended to block and the effects can be removed. Finally, experiment results demonstrate that the issues caused by open-circuit faults can be reduced significantly with the proposed fault-tolerant method.

Direct-Switch Duty-Cycle Control of Grid-Connected n-Level Neutral-Point-Clamped Converter

Capacitor voltage imbalance is a well-recognized issue for neutral-point-clamped (NPC) converters. Hardware solutions increase the system cost and complexity, while existing software solutions generally involve sophisticated algorithms, making it difficult to extend them for more voltage levels and full power factor range. In this paper, a new control method, termed direct-switch duty-cycle control (DSDCC), is proposed and generalized for the grid-connected <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -level NPC ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> L-NPC) converter. This method has the advantages of balancing the capacitor voltages for the full range of power factors on the ac side. The main significance of the DSDCC is that it can achieve near-optimal performance with simple and fast control implementation for two reasons. Firstly, the DSDCC is based on the model directly concerning switches' duty cycles, which can easily generate gating signals for the converter with only one carrier. Secondly, instead of searching for an optimal control solution, near-optimal switch duty-cycles are derived such that the controller design can be greatly simplified. The extremely fast execution time of the proposed control algorithm is only about 3% of that of model predictive control for 5-level NPC converters. Experimental results are included to validate the proposed method with a 5L-NPC converter.

Capacitor‐voltage‐balancing control for isolated medium‐voltage AC‐DC modular matrix converter

AbstractThis paper presents a capacitor‐voltage‐balancing control scheme for an isolated medium‐voltage AC‐DC converter using level‐shifted pulse width modulation (PWM) control of a modular matrix converter (MMxC). The proposed isolated AC‐DC converter is composed of the primary MMxC with level‐shifted PWMcontrol, high‐frequency transformer, and secondary H‐bridge circuits. The high‐frequency transformer of the proposed circuit can be downsized because the level‐shifted PWM control scheme makes the rated frequency of the high‐frequency transformer equal to the switching‐frequency. The proposed capacitor‐voltage‐balancing control can compensate for the capacitor voltage imbalance of the MMxC using the positive‐sequence and negative‐sequence circulating‐currents with a power supply frequency and high‐frequency voltage. In the proposed control system, the three feedback control systems with DC control variables can be developed to compensate for the capacitor voltage imbalance. The effectiveness of the proposed capacitor‐voltage‐balancing control scheme and the control systems is verified by experiments using a 200 V, 5‐kW laboratory prototype.

Capacitor-Voltage-Balancing Control for Isolated Medium-Voltage AC-DC Modular Matrix Converter

This paper presents a capacitor-voltage-balancing control scheme for an isolated medium-voltage AC-DC converter using level-shifted PWM control of a modular matrix converter (MMxC). The proposed isolated AC-DC converter is composed of the primary MMxC with level-shifted PWM control, high-frequency transformer, and secondary H-bridge circuits. The high-frequency transformer of the proposed circuit can be downsized because the level-shifted PWM control scheme makes the rated frequency of the high-frequency transformer equal to the switching-frequency. The proposed capacitor-voltage-balancing control can compensate for the capacitor voltage imbalance of the MMxC using the positive-sequence and negative-sequence circulating-currents with a power supply frequency and high-frequency voltage. In the proposed control system, the three feedback control systems with DC control variables can be developed to compensate for the capacitor voltage imbalance. The effectiveness of the proposed capacitor-voltage-balancing control scheme and the control systems is verified by experiments using a 200V, 5-kW laboratory prototype.

Open-Circuit Fault Diagnosis and Tolerant Control for 2/3-Level DAB Converters

A two-to-three (2/3)-level dual-active-bridge (DAB) converter is a promising dc–dc converter for medium- and high-voltage applications. That is due to its advantages like high power density, galvanic isolation, and capability of withstanding higher voltage ratings compared to the two-level DAB converters. However, the open-circuit fault (OCF) is critical for the 2/3-level DAB converters, resulting in various negative effects, e.g., dc bias, overshoot current, and capacitor voltage imbalance. To address these issues, it is necessary to develop fault diagnosis and fault-tolerant control strategies. This article, thus, proposes a method to identify the faulty switch based on the dynamic characteristics when the OCF occurs. The midpoint voltages of the neutral-point-clamped bridge arms are employed as the fault diagnosis signals, where the faulty switch can be identified accurately based on the mean values and duty cycles of the midpoint voltages. Subsequently, a fault-tolerant control scheme based on a complementary-switch-blocking method is proposed. In this scheme, when the OCF occurs on one switch, the gate-driving signal of its complementary switch is blocked, and the OCF negative effects, e.g., dc bias, overshoot current, and unbalanced capacitor voltages, can be alleviated significantly. Furthermore, the power transfer capability of the 2/3-level DAB converters is enhanced with the proposed scheme compared to the traditional bypass-arm method. Finally, experimental tests are carried out to verify the theoretical analysis.

A Single-Phase Switched-Capacitor Nine-Level Inverter With Reduced Capacitance

A novel nine-level switched-capacitor multilevel inverter (SCMLI) with reduced capacitance and balanced capacitor voltage is proposed in this article. Utilizing only two capacitors, the proposed SCMLI can boost the input voltage and realize nine output voltage levels under different kinds of load conditions. The controllable capacitor charging speed in the proposed SCMLI depends on the charging resonant inductor rather than the equivalent resistance of the devices in conventional topologies. The two capacitors can be charged or discharged independently by a dc source when their voltages deviate from the rated voltage. This makes the proposed SCMLI free of the capacitor voltage imbalance. The longest discharging time (LDT) of capacitors is reduced to twice the switching period, which contributes to reduced capacitance in the proposed SCMLI. With the required capacitor voltage ripple, the quality of output waveforms is also very high. A comprehensive comparison with previous SCMLIs in terms of capacitance, the voltage imbalance problem, the output voltage level, and so on is conducted to validate the merits mentioned above. The theoretical analysis, the simulation, and experiment results are accordant, confirming the feasibility of the proposed SCMLI.

Analysis of Capacitor Voltage Imbalance in Hybrid Converters and Inherently Balanced Operation Using Symmetric Architecture

This letter investigates the origin of the flying capacitor voltage imbalance in hybrid converters. An intuitive voltage–charge relationship is established to give a general explanation of the flying capacitor voltage balance in hybrid converters. The relationship is applied to devise a relatively simple and intuitive method to identify the behavior and performance difference of capacitor voltage and inductor current balancing performance in hybrid converters for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{out}}&lt; \frac{V_{\text{in}}}{N}$</tex-math></inline-formula> cases. Conventional hybrid converters with an even number of inductor charging intervals are shown to be susceptible to flying capacitor voltage imbalance, while flying capacitors in hybrid converters with inductors having odd charging intervals have inherently balanced operations. As a direct result of the analysis, a new symmetric architecture and the operation of three-level buck converters are introduced to achieve an inherent balance of flying capacitor voltages, which can be applied to other flying capacitor multilevel converters. Hardware prototypes are implemented and measured for the verification of the analytical analysis and the new symmetric operation

Corrections to “Dual T-Type Four-Level Converter” [Jun 20 5594-5600

Chen and Wang [1] proposed a dual T-Type four-level converter with a variable-carrier voltage balancing method. The capacitor voltage imbalance mechanism was revealed in [1, Sec. III], with a conclusion that the overdischarge of the middle capacitor is the root cause of the capacitor voltage imbalance issue. This has been experimentally validated by the articles [1], [2]. Although the conclusion is correct, the theoretical derivation of the average capacitor currents is incorrect as the input current and the duty cycle of every power switch were not considered in the previous version. As a correspondence, we would like to present the corrected equations of the average capacitor current calculation in Section III. In addition, there is one more correction to the capacitor voltage ripple description in Section V.

A Modified Neutral-point Voltage Control Strategy for Three-level Inverters Based on Decomposition of Space Vector Diagram

Capacitor voltage imbalance is a significant problem for three-level inverters. Due to the mid-point modulation of these inverter topologies, the neutral point potential moves up or down depending on the neutral point current direction creating imbalanced voltages among the two capacitors. This imbalanced capacitor voltage causes imbalanced voltage stress among the semiconductor devices and causes increase output voltage and current harmonics. This paper introduces a modified voltage balancing strategy using two-level space vector modulation. By decomposing the three-level space vector diagram into two-level space vector diagram and redistributing the dwell times of the two-level zero space vectors, the modified voltage balancing method ensures minimal NP voltage ripple. Compared to the commonly used NP voltage control method (using 3L SVM [9]), the proposed modified NP voltage control method offers a slightly higher neutral-point voltage ripple and output voltage harmonics but, it has much lower switching loss, code size and execution time.

A Cascaded Hybrid Switched-Capacitor DC–DC Converter Capable of Fast Self Startup for USB Power Delivery

Hybrid switched-capacitor (SC) dc–dc converters show promise in applications that require high conversion ratios and small physical size. However, the problem of flying capacitor voltage imbalance, especially during transients, remains a major challenge that limits the adoption of such converters. This article presents a highly integrated hybrid switched-capacitor (SC) converter for universal serial bus (USB) powered applications, featuring fast balancing dynamics. The topology consists of two cascaded stages to increase the conversion ratio. The output voltage regulation and flying capacitor active balance are both achieved by modified ripple injection control (MRIC), with an additional phase skipping technique further improving the transient response during startup. Fabricated in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) technology, the converter prototype has a peak efficiency of 96.9% for 5:1.2 V conversion. Safe startup can be achieved with the input voltage rising from 0 to 5 V within 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> (0.62 V/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> slew rate).

Optimization Scheme Based on High-Frequency Link Interconnection of Submodules

Submodule (SM) capacitor voltage ripple and imbalance are inherent problems with conventional modular multilevel converter (MMC). In addition, the large size capacitance in SM reduces the power density of MMC, and the life defect of electrolytic capacitor also decreases reliability of the converter. This article proposes a modified switched-capacitors based MMC (SC-MMC) topology with ripple-power decoupling channels. Without relying on any closed-loop control, the natural elimination of SMs ripple-power and automatic balance of SMs voltage can be realized simultaneously, which greatly increase the power density and simplify the control design of system. In this article, the ripple characteristic of the conventional MMC and the constraint on capacitance are studied, and an SMs ripple-power decoupling method is analyzed. The power characteristics and impedance constraint analysis of the switched-capacitors are described in detail and the configuration assessments including volume, cost, and efficiency of the SC-MMC are also analyzed. Finally, a down-scaled experimental platform is built, and the experimental results verify the correctness and effectiveness of the proposed scheme.

The new approach minimizes harmonics in a single-phase three-level NPC 400 Hz converter for airplanes

&lt;span lang="EN-US"&gt;This paper provides a new approach to reducing high-order harmonics in 400 Hz inverter using a three-level neutral-point clamped (NPC) converter. A voltage control loop using the harmonic compensation combined with NPC clamping diode control technology. The capacitor voltage imbalance also causes harmonics in the output voltage. For 400 Hz inverter, maintain a balanced voltage between the two input (direct current) (DC) capacitors is difficult because the pulse width modulation (PWM) modulation frequency ratio is low compared to the frequency of the output voltage. A method of determining the current flowing into the capacitor to control the voltage on the two balanced capacitors to ensure fast response reversal is also given in this paper. The combination of a high-harmonic resonator controller and a neutral-point voltage controller working together on the 400 Hz NPC inverter structure is given in this paper.&lt;/span&gt;

A New MMC Sub-Module Topology with DC Fault Blocking Capability and Capacitor Voltage Self-Balancing Capability

A large number of modular multilevel converters (MMC) are connected to HVDC transmission systems nowadays. This paper aims at the short-circuit fault in the DC line of the HVDC transmission system and the problem of capacitor voltage imbalance in MMC, proposing a new type of MMC sub-module, which has both the DC fault self-clearing ability and the capacitor voltage self-balancing ability. This sub-module combines the topology of half bridge and full bridge. It uses the reverse capacitor voltage to forcibly turn off the conducting diode to block the fault current loop. At the same time, the two capacitances charge and discharge states are consistent by utilizing the operating mode of the sub-module. It is possible to directly achieve a self-balancing capacitor voltage without complex balancing voltage control. The MATLAB/Simulink simulation verifies the effectiveness of the DC fault blocking capability and capacitor voltage balance capability of the proposed sub-module.

Step-up switched-capacitor multilevel inverter employing multiple inputs with reduced switches

A large device count, weak boosting capability, and DC voltage imbalance are common issues in conventional multilevel inverters. In this paper, a novel multilevel inverter is presented that can generate the desired number of output levels with reduced devices by using new switched-capacitor circuits (SCCs). The two input sources and capacitors in the SCC can be switched in parallel and series modes. In the parallel mode, the capacitor voltage of the SCC is charged to the DC source voltage, which inherently solves the capacitor voltage imbalance issue without any auxiliary circuits. In the series mode, the capacitor can be used as an alternative source, which helps achieve a high voltage gain. The multiple input sources of the SCC make the proposed topology suitable for application in renewable energy generation systems where several DC sources are available. Instead of an H-bridge module, a structure with two half-bridges and two switches is used as a polarity generation circuit at the load terminal. The input sources of two SCCs can be selected as symmetric and asymmetric patterns, which can result in a great number of output voltage levels. The circuit topology, operational principle, modulation strategy, capacitor analysis, and performance comparisons of the inverter are described in this paper. In addition, experimental results verify the feasibility and validity of the inverter.

Experimental Validation of a Nested Control System to Balance the Cell Capacitor Voltages in Hybrid MMCs

In a hybrid modular multilevel converter (MMC), capacitor voltage balance between the Full-Bridge Sub-Modules (FBSMs) and Half-Bridge Sub-Modules (HBSMs) is only possible when the arm currents are bipolar. For a grid-connected MMC, operating at unity power factor, this is typically only achievable when the modulation index is less than 2. Previous control methodologies, based on open-loop feed-forward compensating currents, have been proposed to operate an MMC with a higher modulation index. However, these solutions do not minimize the compensating currents; they cannot compensate entirely for both the variations in the operating conditions and the parameters typically encountered in a real implementation; and they do not consider the actual capacitor voltage imbalance between the FBSM and HBSMs. In this paper, a new nested closed-loop control algorithm based on an outer voltage control loop with an inner current loop is proposed and experimentally validated. Feed-forward currents are still utilised in the inner loop, but they are calculated using a new optimising algorithm which minimises the required compensating currents. Moreover, to the best of our knowledge, this is the first work where explicit algebraic equations to calculate these compensating currents are provided. Experimental results to validate the approach, obtained with an 18-cell hybrid MMC, are presented and discussed in the paper.

Topology and Voltage-Balance Control of a Single-Phase Active Neutral Point Clamped Seven-Level Inverter

This article proposed a single-phase active neutral point clamped seven-level (SANPC-7L) inverter topology with only eight power switches and three dc-link capacitors. Compared with the existing single-phase seven-level inverters, the quantity of power switches and voltage stresses across them are both reduced. Modulation logic expression of every switch is derived based on the Karnaugh map technique. Like the existing counterparts with three series-connected dc-link capacitors, there is a severe capacitor voltage imbalance issue. This issue is hard to address as there are no redundant switching states that can be selected to balance the dc-link capacitor voltages. This article gives a comprehensive analysis on the capacitor voltage imbalance issue. It indicates that the over charge or discharge of the middle capacitor voltage is the root cause of this issue, while the upper and lower capacitor voltages can be automatically balanced. To overcome this issue, a variable-reference voltage-balance control method is used to enable a three-level voltage waveform to appear in every switching period, and thus the middle capacitor voltage can be controlled at 1/3 of the dc-link voltage. Both the simulation and experimental results have been presented to verify the proposed topology with the variable-reference voltage-balance control strategy.