Voltage-controlled Oscillator Output Research Articles

K‐band CMOS voltage‐controlled oscillator using switched self‐biasing technique

AbstractA complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively.

A Time-Domain Readout Technique for Neural Interfaces Based on VCO-Timestamping.

CMOS neural interfaces are aimed at studying the electrical activity of neurons and may help to restore lost functions of the nervous system in the future. The central function of most neural interfaces is the detection of extracellular electrical potentials by means of numerous microelectrodes positioned in close vicinity to the neurons. Modern neural interfaces require compact low-power, low-noise readout circuits, capable of recording from thousands of electrodes simultaneously without excessive area consumption and heat dissipation. In this article, we propose a novel readout technique for neural interfaces. The readout is based on a voltage-controlled oscillator (VCO), the frequency of which is modulated by the input voltage. The novelty of this work lies in the postprocessing of the VCO output, which is based on generating digital timestamps that contain temporal information about the oscillation. This method is potentially advantageous, because it requires mostly digital circuitry, which is more scalable than analog circuitry. Furthermore, most of the digital circuitry required for VCO-timestamping can be shared among several VCOs, rendering the architecture efficient for multi-channel architectures. This article introduces the VCO-timestamping concept, including theoretical derivations and simulations, and presents measurements of a prototype fabricated in 0.18-μm CMOS technology. The measured input-referred noise in the 300 Hz-5 kHz band was 5.7 μVrms, and the prototype was able to detect pre-recorded extracellular action potentials.

Frequency-Based Sensor Interface with Dynamic Offset Compensation

Sensor interfaces need to be robust and accurate for many applications. This is more challenging for sensor systems operating in radiation environments because the mismatch between components grows as a result of the absorbed total ionizing dose (TID). In frequency-based sensor interfaces, the frequency drift of the voltage-controlled oscillator (VCO) can create dynamic output offset, gain, and linearity errors unless a calibration algorithm is included. In this paper, a digital intensive dynamic offset cancelation technique is proposed for an open loop VCO-based sensor to digital converter, which is achieved by making periodic adjustments to the average center biasing voltage of one of the VCOs in a differential architecture, in effect to make their center frequencies match. A simulation of the behavioral model of the proposed architecture was developed and hardware implementation of the whole system was performed on an FPGA by emulating, with digital modules, the characteristics of the two VCO outputs modulated with differential inputs. The results showed that the output offset error was reduced from around 5% to 0.1% for a relative oscillators’ drift close to 10% of the tuning range, and the SNDR is relatively maintained when subjected to variable relative VCO drifts.

Complementary frequency electromagnetic gyroscope

This paper proposes a complementary frequency electromagnetic gyroscope. In this gyroscope, a voltage-controlled oscillator (VCO) is applied to generate complementary frequency signals and the angular rate detection is realized based on a phase-locked loop. The complementary frequency electromagnetic gyroscope can be fully realized by micro-electronic technology, which is beneficial to the miniaturization of the angular rate measurement system and has a wide application prospect. The complementary frequency electromagnetic gyroscope extends the application of the Sagnac effect and replaces the optical signal with the electromagnetic pulse signal. It can make full use of the advantages of microelectronic technology and microwave technology to realize the miniaturization of measuring components and even realize the system on a chip. In this paper, the mathematical model of the complementary frequency electromagnetic gyroscope is established and verified by simulation analysis. Theoretical analysis shows that the measured angular rate is proportional to the relative frequency difference of complementary VCO output. The simulation results indicate that the sensitivity of the complementary frequency gyroscope is 1 × 10−5 rad/s and is insensitive to noise. When the signal-to-noise ratio is lower than 0 dB, the gyroscope still has good angular rate measurement accuracy.

Phase-locked Loop with True Random Number Generator for Reference Spur Reduction

This paper presents a phase-locked loop (PLL) that reduces reference spurs by using a true random number generator (TRNG). In conventional PLLs, a frequency component of the reference clock appears spurious tones in the voltage-controlled oscillator (VCO) output. In the proposed PLL, the TRNG randomly delays UP/DOWN signals which result in inconsistent timing of charging/discharging at the output of the charge pump (CP). As a result, the CP output disperses the reference spur of the VCO output by making the reference clock frequency component uneven. The proposed PLL was fabricated in a 180-nm CMOS technology. It dissipates 23 mW at 2-GHz with 1.8-V supply and achieves more than 23 dB of additional spur suppression.

Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.

A Compact, Low-Power and Constant Output Power 330 GHz Voltage-Controlled Oscillator in 130-nm SiGe BiCMOS

Nowadays, terahertz and sub-terahertz frequencies are experiencing a significant interest from both academic and industrial world, since they offer a wide and unused spectrum available for different applications, as high-throughput communications, efficient imaging systems and medical uses. In this work an innovative sub-THz voltage-controlled oscillator (VCO) realized with a 130-nm SiGe process is proposed and described in detail. The technology is the SG13G2 bipolar-complementary-metal-oxide-semiconductor (BiCMOS) provided by IHP foundry. The signal source is conceived for high-resolution THz imaging camera; at design level it has been defined with a push-push architecture and adopts an oscillator core based on a Colpitts topology. State-of-the-art performance has been obtained thanks to the proposed design choices that are uncommon at these frequencies, as for instance, the VCO output taken from the common base node, the use of varactors in anti-series connection and the possibility to define a double output at different harmonic frequencies. These, as well as other innovative expedients, allow to simplify the integration at system level and to achieve compact sizes, very low power consumption and almost constant output power level over the full tuning bandwidth. A relative tuning range of about 5.5% has been obtained around a central frequency of 330 GHz, while the output power is about − 8 dBm with a maximum variation of 0.4 dB. Also the phase noise of − 110 dBc/Hz at 10 MHz offset is very promising. Measurements over different chip samples demonstrate the robustness of the proposed solution and the reliability of the design.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A 300-GHz High-Power High-Efficiency Voltage-Controlled Oscillator With Low Power Variation

This letter presents a 300-GHz voltage-controlled oscillator (VCO) with high output power and efficiency. The VCO core employs a differential Colpitts topology with inductive degeneration to facilitate a fundamental oscillation at 300 GHz. A common-base output buffer regulates the output power to minimize the power variation during the frequency tuning. The 300-GHz VCO is fabricated in a 130-nm InP double heterojunction bipolar transistor (DHBT) technology. The VCO exhibits a measured frequency tuning range of 9.9 GHz (294.9–304.8 GHz). The peak output power is measured to be 4.7 dBm at 297 GHz. The dc power consumption is 75.6 mW, leading to a high dc-to-RF conversion efficiency of 3.9%. The VCO output power is maintained nearly constant with only a 0.3-dB variation over the entire frequency tuning range. The phase noise is −86.6 dBc/Hz at 10-MHz offset frequency.

Design of a good oscillation frequency and moderate phase noise current mirror VCO

Abstract This brief presents a good oscillation frequency and moderate phase noise voltage controlled oscillator (VCO) using current mirror topology. Here, a novel VCO using current mirror is designed which increases current in the cross-coupled circuit hence the single-ended output voltage. The width of mirroring transistors is decreased so that the current gain is increased in each branch of differential configuration. It leads to increase in single-ended drain current. Therefore, the close-in phase noise settlement from the enhanced voltage variation at the VCO output due to enhanced current flow in the circuit. The proposed VCO architecture is implemented in 180 nm CMOS process and simulated in Cadence tool. It demonstrates the tuning range of 2.165 to 2.235 GHz and a lower phase noise of -112 dBc/Hz at carrier offset of 1 MHz and -30 dBc/Hz at carrier offset of 1 KHz with a power consumption of 6.71 mW. So, this work will be a proper building block for the design of a customized receiver.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

CMOS Active Inductor/Resonator Based Voltage Controlled Oscillator

Background: A tunable CMOS active inductor/resonator based Voltage Controlled Oscillator (VCO) has been presented. In the design of LC-VCO, LC resonator (tank) circuit has been substituted with gyrator based CMOS active inductor/resonator. The purity of VCO output signal is defined by the phase noise parameter. Methods: For good spectral purity of VCO output signal, the phase noise should be minimum. Moreover, the quality factor of LC resonator is inversely proportional to the phase noise of VCO output signal. In the presented work, a high-quality active inductor/resonator circuit has been used to design VCO which minimizes the phase noise and chip area as well. Further, other VCO characterization factors are measured. Results: The designed circuit has been implemented in 0.18µm CMOS technology. Conclusion: The design of the proposed AI based voltage controlled oscillator shows better phase noise, less chip area and high output power. The high output power is achieved at the cost of limited tuning range of 1.14 GHz ~ 2.1 GHz. The presented active inductor based voltage controlled oscillator can be used for RF applications from 1.14GHz ~ 2.1GHz.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

An energy-efficient multi-level RF-interconnect for global network-on-chip communication

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) using a sub-harmonic multiply-by-10 injection-locked frequency multiplier is also designed to support a fully-synchronous NoC architecture. A differential voltage-controlled oscillator (VCO) used in a PLL creates an output frequency for a frequency range between 0.5 and 2.65 GHz signal. The multiply-by-10 ILFM generates 10 times higher frequency than the VCO output signal. Using the proposed multiply-by-10 ILFM can minimize the number of power-hungry frequency divider stages in a PLL feedback loop, resulting in improvement of the MRI power efficiency. The MLS-based BB and ASK-based RF band carry 10 Gb/s/pin and 4.4 Gb/s/pin, respectively. The proposed system is fabricated in a 65 nm CMOS process and achieves an energy efficiency of 2 pJ/b.

A Multi Output Formulation for Analog Circuits using MOM-SVM

This paper proposes performance based macro modeling of analog circuit using Multi Output Modeling (MOM) with the help of Support Vector Machine (SVM). SVM models the analog circuits and provides a relation between multi-input and multi-output parameters. In this work, Voltage Controlled Oscillator (VCO) is modeled as a test circuit which is designed in Cadence Virtuoso GPDK 45nm technology. From the Spice simulation results, the feasible dataset has been extracted from the complete dataset. Then, the VCO output frequency and phase noise is modeled by the width of the transistors which are the input parameters of the transistors. After tuning the model properly by k-cross validation method, the accuracy was found to be 96.1% which is good enough to make it use for the circuit synthesis purpose.

Comments on “Development of an ANN-Based Linearization Technique for the VCO Thermistor Circuit”

Recently, Kumar et al. [1] have reported an Artificial Neural Network (ANN) based linearization technique for Voltage Controlled Oscillator (VCO) thermistor circuit. In this work ANN was used to linearize the frequency output of VCO, driven by the voltage across thermistor, for an input temperature range of 0 °C–100 °C. Performance of the developed technique was claimed to be experimentally verified for sensitivity and linearity of 5 kHz/°C and ±0.2%, respectively, for all the investigated three different thermistors (M/S Phillips make). In this comment, using the data provided in [1] and based on the relevant theoretical analysis it is shown the obtainable theoretical sensitivities are 136.918 Hz/°C, 108.919 Hz/°C and 267.938 Hz/°C for the used thermistor-1, thermistor-2 and thermistor-3, respectively, instead of the claimed 5 kHz/°C.

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

A 16 MHz, highly stable voltage controlled oscillator (VCO) is reported in this paper. The proposed VCO consists of three cross-coupled RC stages, and is fully compatible with standard CMOS process. A positively biased PN junction with negative temperature coefficient is incorporated in the design to compensate frequency drift. In addition, a delay locked loop (DLL) directly following the VCO is utilized to further improve the output stability caused by temperature variations. The designed circuit was implemented using CMOS 0.18 μm technology, and was validated through experiments. Measurement results show that the DLL-assisted VCO output variation across the 25~120 °C temperature range is less than 0.56 %, corresponding to 59.2 ppm/°C. It also shows that the output standard deviation of the DLL-assisted VCO is only 6.816 KHz, ~ 16.6 % better compared with the same VCO without DLL's assistance.

Optimization of a Particles Detection Chain Based on a VCO Structure

An analysis and optimization of an oscillator based detection chain, dedicated to the conditioning of low input signals, is presented in this paper. The concept is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. In order to improve the correlation between the input current and the oscillator response (signal recognition), the full characterization of the VCO is presented. The solution enhances the particle recognition with a simple analysis of the VCO output. The new output parameter variations are analyzed and the system resolution is explored.

1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application

A spread-spectrum clock generator (SSCG) that is characterized by a low jitter voltage-controlled oscillator (VCO) with a high-frequency limiter and an autocalibration function is developed for a Serial-ATA application. The high-frequency limiter prevents the SSCG from going into an unlocked state. The proposed VCO achieved far less jitter than a conventional one because a proposed structure has fewer operating MOSs that are noise sources. The autocalibration technique calibrates the VCO sensitivity, the maximum frequency of the VCO output signal, and the characteristics of the limit function to prevent the SSCG from degrading an output jitter and an electromagnetic interference (EMI) reduction due to a process variation. The proposed SSCG with the autocalibration function was fabricated in a 0.13-μm CMOS process. The variation in the jitter in 250-cycles at 1.5 GHz with spread-spectrum clocking (SSC) is improved from 2.1-7.8 ps to 1.9-3.3 ps and the EMI reduction is achieved as 10.0 dBm by the proposed autocalibration technique.

An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-$\mu$W Leakage-Compensated PLL and Automatic Quench Waveform Generator

An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.