Voltage-controlled Oscillator Core Research Articles

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Compact and low phase noise LC‐VCO design using novel V‐shaped inductor in 0.18‐μm CMOS technology for Ku‐band applications

SummaryAn innovative, high‐quality factor, and small‐area V‐shaped inductor is presented in this article to improve the performance of voltage‐controlled oscillators (VCOs). The differential inductance of the suggested V‐shaped inductor in the resonator and the buffer is 280 pH and 630 pH, respectively. The inductor area is compacted by 42% and 76% compared to the conventional inductor with the same inductance value. Using 0.18‐ CMOS technology, the proposed V‐shaped inductor is employed to design a compact VCO operating at Ku‐band. The proposed VCO has a simulated phase noise range of −114 to −114.6 dBc/Hz, which is relatively constant. Also, its simulated frequency tuning range (FTR) is 5.6 % from 14.03 to 14.74 GHz. The power consumption is 2.2 mW. The simulated figure of merit (FoM) ranges from −193.5 to −194.2 dBc/Hz, which is enhanced by 6%. The designed VCO core area is 0.034 mm2, which is compacted by 35% compared to using a conventional spiral inductor. The achieved area‐included figure of merit ( ) is −208.7 dBc/Hz. The VCO has an output power of −6.8 dBm and a good harmonic suppression of 29.4 dB between the fundamental and the second harmonic.

Design of a 175 GHZ SiGe-based voltage-controlled oscillator with greater than 7.6 dBm power

<p>In this research, we present a low phase noise (PN) and wide tuning range 175 GHz inductors and capacitors (LC) voltage-controlled oscillator (VCO) based on a differential Colpitts oscillator that was designed using a 0.13 μm bipolar complementary metal oxide semiconductor (BiCMOS) and simulated. The square of the tank Q-factor and the square of the oscillation amplitude were both maximized to reduce PN. With an extensive examination of parasitic, mathematical analysis of load impedances, and implementation of differential design, the PN was reduced, and the output power was enhanced. Using a supply voltage of 1.6 V, the VCO consumes 41.9 mA, resulting in a total power usage of 67 mW to prevent undesirable PN deterioration, an inter-stage LC filter at the VCO-buffer interface increases the swing at the buffer input. To make a better output, a buffer is used to isolate the load from the VCO core. In addition, the VCO has a high linearity and the overall, the VCO presented in this study demonstrates excellent performance and has the potential to be used in a wide range of applications that require a high-performance, low-power VCO.</p>

A 12.3–18.5-GHz Single-Core Oscillator Using a Dual-Mode Variable Inductor With a Tunable Self-Resonant Frequency Technique

This article presents a single-core broadband voltage-controlled oscillator (VCO), employing a dual-mode variable inductor (VID). By configuring two independent switched-capacitor arrays embedded into a magnetically coupled LC network with a moderately magnetic coupled coefficient, the frequency tuning range (FTR) is improved by the wide inductance reconfigurable range of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${X}$ </tex-math></inline-formula> -type mode. Together with 2-bit conventional switched-capacitor banks, the VCO measures an FTR of 40.25% from 12.5 to 18.3 GHz. The low-quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> ) degradation characteristic of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> -type mode is utilized to implement the tuning bands calibration (TBC). After calibration, the tuning voltage can always be calibrated within a small range around the common voltage. The ultimate turning band covers the frequency drift caused by the temperature variation. Designed and fabricated in 65-nm CMOS technology, the measured phase noise after 1/2 division is −114.7 dBc/Hz at 1-MHz offset from the 18.49-GHz carrier frequency. The VCO core exhibits average power dissipation of 9.6 mW from 0.75-V power supply and 0.053 mm2 die area, while the other circuits are powered by a 1.2-V supply.

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

This study reports a voltage-controlled oscillator (VCO) implemented in a 0.18-μm CMOS process. By utilizing an inductive dual-balance source degeneration (IDSD) technique with a current-reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1- and 10-MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures-of-merits (FOMs) of the proposed VCO at 1- and 10-MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.

-Band Class-B VCO in 22 nm FD-SOI With Inductive Source Degeneration of the Tail Current Source

In this work, a voltage-controlled oscillator (VCO) in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band has been introduced that uses the proposed technique named “inductive source degeneration of the tail current source.” The contribution of this work is that the auxiliary resonator is placed differently than the conventional works so that it leads to a more compact solution without affecting the phase noise (PN). Based on the simulation results, for the same device sizes and power consumption, the proposed Class-B method reduces the PN by 1.5 dB than the conventional one at 1 MHz offset from 24 GHz center frequency. VCO has been fabricated on a die area of 0.026 mm2 in the 22 nm fully depleted silicon on insulator (FD-SOI) technology. The measurement was done in the free-running mode, and the results show a PN of −122.4 dBc/Hz at 10 MHz offset from the center frequency of 23.8 GHz. The power consumption of the VCO core is 14.4 mW with 1 V supply voltage. According to the measurement results, this work achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {FoM}_{A}}$ </tex-math></inline-formula> , a figure of merit which considers the VCO core area, of −194.2 dBc/Hz at 10 MHz offset from the center frequency, featuring state-of-the-art among the CMOS VCOs in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band.

Design of 50-GHz Low Phase Noise VCO Employing Two-Branches DGS Resonator in 0.18-μm CMOS Technology

This letter presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and −122.05 dBc/Hz (−102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of −189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band and beyond.

A noise circulating VCO with an intrinsic injection locking tripler

AbstractA noise circulating voltage‐controlled oscillator (VCO) with an intrinsic injection locking tripler is introduced. Based on the conventional frequency tripling scheme, by integrating the injection transistor pair into the fundamental VCO core, the current of the fundamental VCO core is reused by the injection transistor pair, and the phase noise is reduced due to the noise circulating behavior. The proposed VCO may achieve the fundamental and 3rd harmonic outputs, simultaneously. A protype design is implemented in a standard 65 nm CMOS process, with a tuning range of 33.68–40.11 GHz (17.4%). The phase noise at 1‐MHz offset varies between −101.2 and −97.9 dBc/Hz among the tuning range. The FoMT is in the range of 190.4 and 187.9 dBc/Hz, at 1‐MHz offset.

Phase Noise Reduction in LC VCO’s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FoM}}_{A}$ </tex-math></inline-formula> , is 209 dBc/Hz.

Low‐power dual‐band voltage‐controlled oscillator using a fourth‐order resonant technique

AbstractA low‐power dual‐band voltage‐controlled oscillator (VCO) using a fourth‐order resonant technique implemented in 0.18‐μm CMOS process is presented in this letter. By utilizing a fourth‐order LC‐type resonant network and a current‐reused technique, the proposed VCO operates in the dual‐band mode and improves the overall performance. The tuning ranges of band 1 and band 2 are from 3.39 to 3.68 GHz and from 7.2 to 7.57 GHz controlled by a controlled‐voltage VC, respectively. The measured phase noises at 1 MHz frequency offset are −117.39 dBc/Hz and −113.58 dBc/Hz for output frequencies of 3.68 and 7.21 GHz, respectively. Besides, the figures‐of‐merit (FOM) at 3.68 and 7.21 GHz output frequencies are −182.5 and −184.5 dBc/Hz, respectively. The proposed VCO core consumes 4.2 mW from a 1.2‐V supply.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

An Ultra-Compact Multi-Band VCO Achieving − 196 dB FoMA with Single-Ended Tunable Active Inductor

This paper presents a wide tuning-range LC-tank voltage controlled oscillator (VCO). To perform large frequency tuning range, the proposed circuit topology uses a tunable active inductor (TAI) for the coarse frequency tuning, while the fine-tuning is controlled only by a MOS varactor. The TAI design is based on toggling varactor arrays by which four channels are able to be selected for multi-band applications. The proposed VCO is designed in 90-nm CMOS process. Simulation results show that the VCO can operate from 760 MHz to 4.370 GHz representing an FTR of 140.74%, with a tuning gain Kvco from 654 to 1882 MHz/V. The achieved phase noise is lower than − 105 dBc/Hz at an offset frequency of 1 MHz from the carrier tuned to 2.52 GHz. The VCO core circuit draws 3.3 mA from a 1V voltage supply and occupies a small active area of (45 × 37) μm2. The fully implemented VCO provides excellent performances such as attractive FOMA value of − 196 dBc/Hz.

A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications

This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divide-by-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of −94.7 dBc/Hz at the 1-MHz offset and an output power of −3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of $2.7\times3.1$ mm2.

A 65–81 GHz CMOS Dual-Mode VCO Using High Quality Factor Transformer-Based Inductors

This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOMT are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is 0.146 ×0.205 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Analysis and Implementation of High-Q CT Inductor for Compact and Wide- Tuning Range Ku-Band VCO

This work presents a new structure of center tap (CT) inductor to improve the performance of Ku-band voltage-controlled oscillators (VCOs). Conventional CT inductor provided by the foundry suffers from a poor-quality (Q-) factor large area and low self-resonance frequency. These problems are solved by introducing a coupling structure. For the proposed CT inductor, despite its size is miniaturized by 51%, the Q-factor is increased by 41% in the frequency range of 5-30 GHz compared to a conventional CT inductor. The measured differential inductance and quality factor of the proposed inductor are 385 pH and 22 at 12 GHz. The proposed CT inductor is used to design a compact and wide-tuning-range VCO at Ku-band in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology, and this leads to 5.8 dB phase noise improvement compared to the use of a conventional CT inductor. The fabricated VCO has a compact core size of 140 μm × 400 μm only. The VCO chip oscillates from 11.7 to 13.7 GHz. The measured phase noise is -107.7 dBc/Hz at 1-MHz offset frequency at a carrier frequency of 13.7 GHz, and the dc power consumption of the VCO core is 4 mW which results in a figure of merit (FoM) normalized to the die area (FoMA) to be -197 dBc/Hz.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

New 20 GHz push–push common‐collector Colpitts VCO

A wide-band push–push common-collector Colpitts voltage-controlled oscillator (VCO) usingimpedance peaking network and gain enhancing technique is proposed in this work.The impedance peaking network is introduced to increase the coupling factor ofthe differential inductor in the inductorcapacitor (LC) tank without sacrificing the quality factor. The impedancepeaking technique could guarantee the push–push VCO unconditionally oscillatingin a differential mode without degrading the phase noise performance. The gainenhancing technique employs an LC resonator in series with the emitterdegeneration resistor in the common-collector amplifier in the VCO core toimprove the VCO oscillating amplitude and then improve the phase noiseperformance. The proposed VCO oscillates at around 20 GHz with >10.5%frequency tuning range from 18.9 to 21.4 GHz across temperature from −40 to125°C. The measured phase noise is lower than −107 dBc/Hz at 1 MHz offset acrossthe entire working temperature (−40 125°C). The whole VCO dissipates 45 mA under3.3 V power supply, and the typical figure of merit is around −177.92.

A 300-GHz High-Power High-Efficiency Voltage-Controlled Oscillator With Low Power Variation

This letter presents a 300-GHz voltage-controlled oscillator (VCO) with high output power and efficiency. The VCO core employs a differential Colpitts topology with inductive degeneration to facilitate a fundamental oscillation at 300 GHz. A common-base output buffer regulates the output power to minimize the power variation during the frequency tuning. The 300-GHz VCO is fabricated in a 130-nm InP double heterojunction bipolar transistor (DHBT) technology. The VCO exhibits a measured frequency tuning range of 9.9 GHz (294.9–304.8 GHz). The peak output power is measured to be 4.7 dBm at 297 GHz. The dc power consumption is 75.6 mW, leading to a high dc-to-RF conversion efficiency of 3.9%. The VCO output power is maintained nearly constant with only a 0.3-dB variation over the entire frequency tuning range. The phase noise is −86.6 dBc/Hz at 10-MHz offset frequency.

A Modified Darlington-Based Class-C VCO With Simultaneous Optimization of Phase Noise/FoM in GaAs Technology

This letter presents a modified Darlington-based (DB) class-C voltage-controlled oscillator (VCO) topology which achieves a cooptimization of phase noise and figure of merit (FoM) in GaAs technology. Both the Darlington pair and noise shifting techniques are introduced to improve the phase noise in class-C VCOs. Balanced and differential architectures are used to absorb the strength of both the Colpitts and class-C VCO topology with a simple trick of two cascaded stages in the VCO core, which elevates the VCO driving capability with no degradation of power efficiency. In addition, the startup conditions and capacitive feedback factors are derived and compared in both mathematical and simulation manners, which proves the superiority of the topology. The proposed VCO is fabricated in a GaAs bipolar high electron mobility transistor (BiHEMT) technology which demonstrates a frequency range of 2.76–2.91 GHz with a current consumption of 9.5 mA at 5 V supply, a phase noise of −138.6 to −135.9 dBc/Hz at 1 MHz offset from the carrier, an output power of −3.06 to −4.18 dBm, and a peak FoM of −191.2 dBc/Hz at 1 MHz offset. To the best of the authors’ expertise, the proposed DB class-C VCO achieves both exceptional phase noise and FoM, which far outweigh that of the existing GaAs.

Design of a CMOS 65‐nm inductor‐less VCO for ISM applications in the VHF band

SummaryThis paper presents a design of a CMOS cross‐coupled voltage‐controlled oscillator (VCO) using active inductors (AIs) for wide‐band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator‐C topology as the basic structure to generate an inductance. The VCO uses a cross‐coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65‐nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1‐MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm2 including the pads. The proposed AI‐VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.