Voltage-controlled Delay Line Research Articles

A 0.9 V high‐speed dynamic bias latch‐type comparator employing a voltage‐controlled delay line

AbstractThis paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage.

A 1.11 mm2 IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming at 40 MHz.

Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between ~0 and 10 ns in two directions, generating a steerable plane wave in a range of ±/-50° for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm × 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

A 14 GHZ DELAY LOCKED LOOP WITH MINIMIZED PERIOD DELAY ERROR AND WORST 1.5% DUTY CYCLE ERROR

In many applications, the Delay Locked Loop (DLL) is used to improve the timing margin for better performance of the synchronous system. A precise 50′ duty ratio of the clock signal is essential to the DDR SDRAM, which needs both the rising edge and the falling edge of the clock to sample the data. The duty mismatch of the output clock in the DLL may be caused by the duty error of the external input clock or by the common mode voltage offset in the voltage-controlled delay line (VCDL). Many studies have presented the duty cycle corrector (DCC) to reduce the duty mismatch of the clock. This paper proposes a high-frequency DLL that generates multiplate clocks with a wide frequency range. The object of this research is to have +-1.5% duty cycle error at the output clock and, in locked state, less than 2% of clock period delay between 0- and 360-degree phases (delay error). This generator produces 8 phases at 14 GHz.

A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges

A radiation-hardened delay-locked loop (DLL) applied for multiple frequency ranges is proposed in this paper. Novel and effective radiation-hardened techniques are applied in charge pump (CP) and voltage-controlled delay line (VCDL) to avoid inverted lock error and missing pulses error caused by single-event transient (SET). In order to ensure a wide operation frequency range, a frequency detection module is designed to detect the frequency of input signals and adjust the current source array of VCDL so as to change its delay time. Besides, an accelerate module is designed to reduce the lock time of DLL by providing an extra discharge current. According to the simulation results, the proposed DLL shows good performance when ion strikes occur and can work properly in a wide operation frequency range from 3.7[Formula: see text]GHz to 7.4[Formula: see text]GHz. Also, the proposed accelerate module helps to reduce lock time by 22.2%.

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS

We present a low-power and low jitter two-stage 2.46&#x2013;4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a <inline-formula> <tex-math notation="LaTeX">$64\times $ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">$128\times $ </tex-math></inline-formula> clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs_rms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving &#x2212;53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fs_rms at 4.92 GHz, &#x2212;28.2-dBc reference spur, and 3-mW power consumption.

A delay cell with duty-cycle correction and parasitic compensation for large array indirect time-of-flight CMOS image sensors

Large array indirect time-of-flight (ToF) CMOS image sensors use a self-compensating voltage-controlled delay line (VCDL) to decrease the peak current of the demodulation circuit. However, the ToF detection error is affected by the output duty cycle of the self-compensation VCDL. This paper analyzes the relationship between the output duty cycle of the self-compensation VCDL and the ToF detection error. A delay cell with duty cycle correction and parasitic compensation is proposed. A phase interpolator is also used to improve the output phase resolution of the self-compensating VCDL. This design is implemented using the 0.11μm CMOS process. The post-simulation results show that the correction range of this design is 0.9% to 98% at 100 MHz. By applying the proposed delay cell to the self-compensating VCDL, the delay of one delay cell is reduced by 163 ps due to the parasitic compensation circuit. Moreover, the ToF detection error decreases by 2.03 cm compared to the traditional structure.

A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator

This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20&#x2013;200 kS/s. The designed ADC is fabricated in a 0.18- <inline-formula> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}$ </tex-math></inline-formula> CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.

A 1.2 GHz jitter-peaking-free Integer-N PLL

In conventional charge-pump PLLs, if the third high-frequency pole is ignored, the system comprises of two poles and a zero. The transfer function of such a system is second-order low pass, which in some part of its frequency spectrum, the amplitude response |H| goes above unity. This translates to jitter-peaking, which in turn amplifies the input phase noise. Depending on damping factor or ζ, this jitter-peaking could be large or small. In this paper, a dual-path PLL with an additional Voltage Controlled Delay Line (VCDL) is presented that removes the jitter-peaking by adjusting the frequency values of the zero and poles in the PLL transfer function. In this new architecture, by increasing the VCO's gain (Kvco) the output phase noise is reduced. Designed and simulated in 65 nm CMOS and operating with a reference frequency of 12.5 MHz, the proposed PLL provides a spur level of −45dBc. The presented PLL exhibits an in-band phase noise of −117dBc/Hz at 1 MHz offset and total power consumption of 10.5 mW.

Simulation studies on the transient dose rate effect of analog delay locked loops

This paper presents the transient dose rate (TDR) effect of analog Delay Locked Loops (DLLs). The analog DLL circuits are built upon a previous design, and the typical photocurrents are calculated by the Sentaurus TCAD. Both single double-exponential and dual double-exponential functions are successfully introduced to fit the different photocurrent waveforms with change of the simulated nodes, which then are integrated into the SPICE models for later circuit simulations. Firstly, the radiation effect of individual sub-circuits (e.g. charge pump) and their coupling relationships are analyzed. The simulation results show that the current-charge pump as the most sensitive module can result in the biggest clock error, followed by the voltage-controlled delay line; although the global radiation effect of DLL (use current-charge pump) is almost the same with the individual current-charge pump exposed to the radiation, there are still some coupled relationships exhibiting among modules. Also, the simulation results are qualitatively consistent with previous experiment phenomena; further, it is demonstrated that the voltage-charge pump technique can be used effectively to improve the TDR effect of the charge pump; lastly, the effect of global photocurrents on the rail span collapse is indirectly considered through power analysis. However, it is found that this effect can be negligible due to the very small variation of power.

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links

Without any dummy element for phase compensation, a clock-deskewing circuit (CDC) using a master–slave delay-locked loop (MSDLL) configuration is presented to synchronize the clocks for cascaded core-to-core links. The dual-locking CDC provides mismatch-insensitive compensation of interconnected wires, input/outputs (IOs), and clock buffers. The MSDLL incorporates the digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) to provide a wide range operations. The proposed FCF-VCDL scheme is constructed from the combination of positive and negative gains of different VCDLs. In addition, a power-controlled regime is employed in the FCF-VCDL to adaptively lower the power dissipation. Implemented with 0.18- $\mu \text{m}$ CMOS, the CDC can provide 20 MHz to 2 GHz with the help of FCF-VCDLs. The 2-GHz clock jitter is 6.78 ps (pk-pk), and the total power dissipation is 20 mW under a 1.8-V supply.

A low power and jitter delay cell with pulse width modulation for wide range delay lock loops

To reach a delay lock loop (DLL) with low jitter and power for wide range frequency applications, the performance of delay cell used in the voltage-controlled delay line (VCDL) play the most important role. In recent years, a variety of methods have been proposed to achieve a wide-range delay cell. In this paper, a method is proposed in which pulse width modulation (PWM) technique is used to generate a wide-range delay it is in a better trade-off with power and jitter with respect to previous work. PWM circuit creates two control signal (rising and falling control signal) for last stage transistors. These control signals generate a signal that is similar to the input signal of the delay cell with a controllable delay. The proposed delay cell is able to generate a delay that is more than half of the input clock period leads to a wideband DLL. The delay cell has been simulated in TSMC RF CMOS 0.18 μm technology at 1.8 V supply voltage. The simulation results show that the desired structure has a delay range of 195 ps to 3.4 ns in a frequency range 300 MHz to 1 GHz. Moreover, its RMS jitter is equal to 2–22 ps, 0.33 ps at 300 MHz and 1 GHz, respectively.

28nm FDSOI Ultra Low Power 1.5–2.0 GHz Factorial-DLL Frequency Synthesizer

This brief presents the design of an ultra-low-power frequency synthesizer based on a feedback loop composed of an improved version of the Factorial Delay-Locked Loop (F-DLL). Its output frequency is controlled by a set of current-starved delay units tuned by a standard DLL feedback loop and a set of logic circuits to generate an RF output frequency proportional to the reference. The objective of this circuit is to achieve a power consumption in the micro-watt range to generate the desired output frequency proportional to the reference frequency between 1.5 and 2.0 GHz, being capable of supporting a wide range of input frequencies with a low phase noise (lower than −90 dBc/Hz at 1 MHz offset) and $370~\mu \text{W}$ of power consumption. In order to ensure the locking state of the feedback loop and to reduce the phase noise, a modification of the biasing circuit for the voltage-controlled delay line (VCDL) is used to improve the linearity of the frequency response of the output using a complementary feedback loop architecture. The circuit was designed and fabricated using the 28 nm FDSOI technology from STMicroelectronics and the measurement results are presented.

A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter

This paper presents a low jitter multiplying delay-locked loop (MDLL) with static phase offset elimination (SPOE) applied to time-to-digital converter (TDC). To reduce static phase offset (SPO) between the reference clock and the output feedback clock, a SPOE techniques based on time amplifier (TA) is proposed, which the reference clock can be accurately injected for timing or phase calibration. The logic selector (LS) used a simplified form to complete mode switching with faster response times. The improved phase detector (PD) implements direct phase discrimination between the output feedback clock and the reference clock. The improved voltage-controlled delay line (VCDL) also makes the MDLL implementing a uniform split-phase output characteristic. The test chip is designed and fabricated in TSMC 0.35-μm 3.3 ​V complementary metal-oxide-semiconductor (CMOS) process which occupies a core area of 0.26 ​mm2. The measurement results show that the output clock jitters at 320 ​MHz frequency is 3.17 ps for root mean square, with the multiplication ratio of 8. The circuit has eight split-phase output clocks with a uniform separation within 45° ​± ​3.4°.

A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL's) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard 0.18μm CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than 16μs. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage.

PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

Exploiting uncertain timing information in time‐based SAR ADCs

Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter

Time-domain operational amplifier (op-amp) is developed with only time-domain circuits such as voltage-controlled oscillator (VCO) and voltage-controlled delay line (VCDL). The infinite dc-gain of the voltage-to-phase transfer characteristic of VCO allows the time-domain op-amp to have large dc-gain. The frequency compensation is performed by the left-half plane (LHP) zero created by VCDL whose output phase is proportional to its control input voltage. With the proposed time-domain op-amp, a fourth-order continuous-time (CT) analog filter with 25 MHz cut-off frequency has been implemented in a 65 nm CMOS technology. The filter occupies 0.107 mm2and operates with 0.9 V supply consuming 8.2 mW. The measured in-band input third-order intercept point (IIP3) is 22.6 dBm and the peak signal-to-noise+distortion ratio (SNDR) is 60.9 dB.