Volt Supply Voltage Research Articles

Penguat Jembatan dengan Untai Pembalik Fase

The maximum output voltage of the audio amplifier is limited to the magnitude of the power supply voltage of the power transistor or the operational amplifier on the final amplifier. This limits the maximum power of the audio amplifier output. The way to enlarge the output power of the audio amplifier without increasing the voltage is the bridge method or bridged modes. With this method a bridge amplifier will be generated. This Bridge Amplifier is also known as Bridge-Tied Load (BTL) or Bridged Transformerless. The principle of Bridge Amplifiers is to use a pair of final amplifiers whose outputs have opposite phase each other. There are 3 ways to make a pair of power amplifiers have opposing phases: with internal modification, with an audio transformer (phase splitting audio input transformer) and with a simple active phase reversal splitter circuit). This paper will discuss Bridge Amplifiers with simple phase inverting circuits. A pair of audio power amplifiers using two TDA2050 chips which are operated at ± 19 Volt supply voltage. The phase inverting circuit using IC TL072. Sinusoidal signal with an amplitude of 200 mVp and a frequency of 1 KHz is used as an input signal. The results to be observed and measured are gain, input, output and bandwidth of the bridged amplifier compared to the usual amplifier

90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate

The Substitution-BOX is the most difficult architecture and is at the heart of any Advanced Encryption Standard algorithm implementation. It is the most complicated non-linear architecture using multiplicative inverse. It consumes maximum amount of the energy and power budget of the algorithm. This paper introduces a full-custom CMOS implementation of Multiplicative Inverse module for Substitution/ Inverse Substitution transformation in composite field arithmetic using Galois field GF (28). The multiplicative inversion module utilizes large number of XOR gates in its implementation. This paper introduces implementation of a novel XOR gate using six transistors. Using this six transistor XOR gate, the multiplicative inverse module is implemented in 90 nm CMOS technology. Simulation of the proposed design is achieved using Tanner EDA v.16 software. The area of the multiplicative inverse circuit is 39.92 µm2 requiring 776 transistors. With 0.6 Volts supply voltage, the design shows a power dissipation of 2.386 µWatts making it ideal for applications such as smart cards and RFID tags.

Design and implementation of a 350-watt BLDC motor driver using an Insulated Gate Bipolar Transistor (IGBT)

IGBT device was not commonly used as a BLDC motor speed controller. This paper described the successful of using IGBTs in a 350Watt BLDC motor speed controller. Triple bridge configuration with PWM (Pulse Width Modulation) wave signal for power tuning was mainly integrated as a main switching method in order to drive the current commutation cycle. Also, an efficient bootstrap IC was designated to perform as the high and low side driver. The data were measured by using a current sensor and a DC voltage sensor to measure the current and the voltage delivered from the power source. Then, IGBT device was activated based on triple bridge commutation cycle and phase based on motor hall effect sensor triggering signal. The performance was also tested by varying the duty cycle input ratio and its PWM frequency. It can conclude that the BLDC motor controller can be made by using an IGBT and added gate drivers for the IGBT. Meanwhile, to adjust the commutation cycle, a high speed processor was used to generate gate activation and PWM signal. Changing the PWM duty cycle starting from 10% to 90% by turning the setting point, observed that BLDC motor rotates successfully without load and maximum power used was 111.20 watts with 2,32 amperes current at 48 volts supply voltage.

Survey on Single Stage Amplifiers for Column Drivers in Active Matrix LCD Panels Leading to a Highly Linear Rail-to-Rail Robust Amplifier

This paper reviews single stage amplifiers identified in the literature as well as presents a new structure single stage highly linear rail-to-rail amplifier intended for column drivers in Active Matrix Liquid Crystal Display (AMLCD). The new proposed amplifier is based on applying current splitting technique on a rail-to-rail differential pair thus elevating the overall performance of the amplifier in terms of different performance parameters such as effective transconductance, output resistance, DC gain and unity gain frequency among others. One major advantage of the new proposed amplifier is its capability of providing a rail-to-rail stable operation without the need for compensation. The performance of the new proposed amplifier is tested on LTspice using 90nm CMOS technology under 1 Volts supply voltage and compared to other existing single stage amplifiers. Simulation results shows that the proposed amplifier provides a high DC gain, high effective transconductance and high output resistance while maintaining a stable operation with a phase margin of 80°. Obtained results also confirms that the amplifier exhibits rail-to-rail operation while maintaining a very low Total Harmonic Distortion (THD). The pulse response of the proposed amplifier indicates a fast response with a rise time and fall times almost twice as fast as the other examined topologies. Against Process, Voltage and Temperature (PVT) variations, the amplifier exhibits a robust performance as the DC gain variation range was within 20% only which is much less than the other examined topologies.

A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product (PDP) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency (fmax.) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance.

Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL Application

The Phase Frequency Detectors (PFD’s) are proposed in this research paper by using the two different structures of D Flip-Flop that is the traditional D Flip-Flop and modified D Flip-Flop with a NAND gate which can overcome the speed and area limitations of the conventional PFD. Both of the PFD’s use 20 transistors. The traditional PFD consumes 133.92 μW power when operating at 40 MHz frequency with 1.8 Volts supply voltage whereas the modified PFD consumes 100.51 μW power operating at 40 MHz frequency with 1.8 Volts supply voltage. The designs are implemented by using 0.18 meter CMOS process in Tanner 13.ov. These can be used in PLL for high speed applications.

Comparative Analysis of Process Variation on Single Bit Domino Full Adder with Single Bit Static Full Adder

Testing and planning of very large scale integration circuits are the most challenging aspects now days, whenever a chip manufacture takes place many important parameters like doping of substrate, channel length of gate oxide and the thickness of the oxide vary during the fabrication of VLSI circuits that has an adverse impact on the circuit performance. In this paper, we demonstrate nearer examination of process variation on single bit domino full adder with single bit static full adder. This paper shows the variation of threshold voltage, oxide thickness and channel length on the execution parameter of single bit full adder that is designed by using a different transistor count like 10T, 28T, 22T. The result demonstrates that when 8.33% variation takes place in channel length than 2.078% increment in the power and 0.132% decrement in delay and 1.75% increase in power delay product of 22T domino full adder circuit, that is a minimum variation when compared with other single bit static full adders 10T and 28T. In threshold voltage when 1.6% variation occurs, then 0.76% decrement in power and 0.76% decrement in power delay product of 22 transistor domino full adder circuit, that is a minimum variation when compared with other single bit static full adder 10T and 28T. In oxide thickness 14.28% variation takes place, then 0.76% reduction in power and 2.49% decrement in PDP of 22T domino full adder circuit that is a minimum variation when compared with other single bit static full adder 28T and 10T. All simulations are done by using the tanner tool with 90nm PTM technology node with 1.1 volt supply voltage.

A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS

In this paper, a 16-phases 20MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35µm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3Volts supply voltage is subject to 75mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small active area, around 380µm×210µm including the clock generation circuit, which is proper to be repeatedly used inside the chip.

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is −21 dBm and −56 dBm, respectively. Measured input IP3 is −12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm2 chip area. The filter is realized in a standard 11 GHz f_t bipolar technology.

InP-HBT ICs FOR 40 Gb/s OPTICAL LINKS

InP-based HBT technology has proven to be a strong candidate for ultra high speed electronic as well as optoelectronic integrated circuits. The cut-offs frequencies of the available devices exceed 100 GHz. To challenge the technology, a variety of circuits, suitable for a demonstrator for the 40 Gb/s fiber optical transmission system have been designed, fabricated, and tested. All the circuits show potential for 40 Gb/s applications. The electrical parts have been implemented in MSI/LSI AlInAs/InGaAs-HBT technology, while the monolithic optoelectronic receivers were realized in SSI- InP/InGaAs HBT technology. The verification of performance of the circuits have been mainly limited by available measurement equipment. All the electronic parts were operational with 3 volt supply voltage. All the circuits were fully functional after the first processing round. No redesign was necessary.

Precise voltage to frequency converter for telemetry applications of strain gage pressure transducers.

A voltage to frequency converter suitable for telemetric applications of strain gage pressure transducers is described and analyzed. The circuit uses a voltage reference IC and a temperature dependent op amp bias current to achieve zero pressure offsets less than 3 torr over a 25°C temperature range and a 1 volt supply voltage range.

Stable Transistor Oscillator

Frequency stability is an essential requirement for most transistor oscillators as for many other oscillators. However, unlike vacuum tube oscillators, transistor oscillators usually suffer a great change in frequency with variation in operating characteristics. The most serious causes of frequency instability are the effect of temperature on parameters of transistors and the variation of supply voltage. By using certain circuit arrangements and a crystal as frequency-controlled element, a high degree of stability could be achieved over a wide range of temperature and supply voltages. As a practical example, a simple crystal controlled 100 kc oscillator is described, capable to deliver 3 volts rms, from supply voltage 12 volts. The frequency stability of the oscillator is better than 10 parts per million per 1 volt supply voltage, and two parts per million per degree centigrade, for a wide range of load resistance ranging from a few ohms to 100,000 ohms. At a frequency of 1 mc, a stability better than 5 parts per ten million per 1 volt supply voltage and one part per ten million per degree centigrade was obtained.