Volatile DRAM Research Articles

GeTe/Sb2Te3 Super‐Lattices: Impact of Atomic Structure on the RESET Current of Phase‐Change Memory Devices

AbstractPhase change memories (PCMs) are at the heart of modern memory technology, offering multi‐level storage, fast read/write operations, and non‐volatility, bridging the gap between volatile DRAM and non‐volatile Flash. The reversible transition between amorphous and crystalline states of phase‐change materials such as GeTe or Ge2Sb2Te5 is at the basis of PCM devices. Despite their importance, PCM devices face challenges including high power consumption during the RESET operation. Current research efforts focus on improving device architecture and exploring alternative phase‐change materials such as GeTe/Sb2Te3 super‐lattices (SLs), for which a reduced programming power consumption is observed compared with standard PCMs. Herein, by combining X‐ray diffraction and scanning transmission electron microscopy imaging of SL thin films with the study of the same SL in PCM devices, it is shown that it is possible to significantly decrease RESET energy of the device, without modifying the SL composition, by reducing the amount of structural defects through annealing treatment. The best device properties are obtained after transforming the SL into a defect‐free, highly out‐of‐plane oriented rhombohedral phase. These results offer a promising avenue for further improving the performance of SL‐based PCM devices through structural optimization.

Evaluating persistent memory range indexes

Persistent memory (PM) is fundamentally changing the way database index structures are built by enabling persistence, high performance, and (near) instant recovery all on the memory bus. Prior work has proposed many techniques to tailor index structure designs for PM, but they were mostly based on volatile DRAM with simulation due to the lack of real PM hardware. Until today is it unclear how these techniques will actually perform on real PM hardware. With the recent released Intel Optane DC Persistent Memory, for the first time, this paper provides a comprehensive evaluation of recent persistent index structures. We focus on B + -Tree-based range indexes and carefully choose four representative index structures for evaluation: wBTree, NV-Tree, BzTree and FPTree. These four tree structures cover a wide, representative range of techniques that are essential building blocks of PM-based index structures. For fair comparison, we used an unified programming model for all trees and developed PiBench , a benchmarking framework which targets PM-based indexes. Through empirical evaluation using representative workloads, we identify key, effective techniques, insights and caveats to guide the making of future PM-based index structures.

Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

Fabrication and Application of Highly Stretchable Conductive Fiber‐Based Electrode of Epoxy/NBR Electrospun Fibers Spray‐Coated with AgNW/PU Composites

AbstractStretchable fiber‐based electrodes are highly desired for the applications of wearable electronics owing to their good durability, excellent deformability, and easy attachment onto a curved surface in comparison with thin film electrodes. However, it is a critical challenge to fabricate a fiber‐based electrodes with low surface roughness and high conductivity under a large mechanical strain. In this study, the fabrication of stretchable and conductive epoxy/NBR‐20 fiber, spray‐coated with silver nanowire/waterborne polyurethane composite, is demonstrated via the combination of electrospinning and spray‐coating techniques. Such a fiber‐based electrode can maintain low resistance (less than 150 Ω) by stretching up to 40% strain and sustain at 30% strain for 200 stretch/release cycles. The deformable conductive fibers can serve as a promising fiber‐based bottom electrode for resistive memory devices and show volatile DRAM characteristics with an ON/OFF memory ratio of 102.

DWARM: A wear-aware memory management scheme for in-memory file systems

Emerging non-volatile memories (NVMs) are promised to revolutionize storage systems by providing fast, persistent data accesses on memory bus. A hybrid NVM/DRAM architecture that combines faster, volatile DRAM with slightly slower, denser NVM can harness the characteristics of both technologies. In order to fully take advantage of NVM, state-of-the-art in-memory file systems are designed to provide high performance and strong consistency guarantees. However, the free space management schemes of existing in-memory file systems can easily cause “hot spots” when updating data structures on NVM, leading to significant skewness in terms of writes to each data page.In this paper, we propose dynamic wear-aware range management (DWARM) scheme, a novel free space management technique for in-memory file systems. This scheme achieves wear-leveling with high performance for allocation/deallocation. The essential idea is to allocate less-written pages for each allocation request. Specifically, this scheme works by associating a write counter with each data page and updating the counters in the file write path. We build an “index” structure to fast locate the pages that have received less writes. The index divides the NVM pages into different subranges according to the write counters. Allocation always starts from the minimal subrange. Also, we propose Adaptive Wear Range Determination Algorithm to adjust the wear ranges dynamically. To accelerate lookup, we keep the index in DRAM and avoid the overhead of strong consistency by rebuilding the index in case of system failure. Experimental results show that this scheme can provide 4.9× to 158.1× wear-leveling improvement compared to the state-of-the-art memory management schemes. For application workloads, the DWARM strategy can improve the lifetime of NVM by up to 125×, 39×, and 25×, compared with the standard memory management schemes of PMFS, NOVA and SIMFS.

A persistent lock-free queue for non-volatile memory

Non-volatile memory is expected to coexist with (or even displace) volatile DRAM for main memory in upcoming architectures. This has led to increasing interest in the problem of designing and specifying durable data structures that can recover from system crashes. Data structures may be designed to satisfy stricter or weaker durability guarantees to provide a balance between the strength of the provided guarantees and performance overhead. This paper proposes three novel implementations of a concurrent lock-free queue. These implementations illustrate algorithmic challenges in building persistent lock-free data structures with different levels of durability guarantees. In presenting these challenges, the proposed algorithmic designs, and the different durability guarantees, we hope to shed light on ways to build a wide variety of durable data structures. We implemented the various designs and compared their performance overhead to a simple queue design for standard (volatile) memory.

Fluorene, pyrene, and thiophene-based donor-acceptor asymmetric small molecules for solution-processable memory performance

In this paper, two new asymmetric donor-bridge-acceptor molecules (PFTCH and PFTCE) containing the same electron donor (pyrene group) and bridge (fluorene group) but different terminal electron acceptors (cyanoacetic acid for PFTCH and ethyl cyanoacetate for PFTCE) have been synthesized and characterized by NMR, HR-MS etc. Their photophysical properties including Uv-vis absorption and emission spectra were studied. They were further used as the memory active materials and the ITO/PFTCH or PFTCE/Al sandwich memory devices were prepared, in which the organic films were obtained by solution process. The I-V measurements display satisfactory memory performance; they have a low threshold voltage, high ON/OFF ratio (106) and a low current value (10−4 A) at the ON state. Although the electron-withdrawing ability of the cyanoacetic acid group is stronger than that of the ethyl cyanoacetate group, the two memory devices (ITO/PFTCH/Al or Au and ITO/PFTCE/Al or Au) display different memory behaviors (volatile DRAM for ITO/PFTCH/Al or Au devices and nonvolatile WORM for ITO/PFTCE/Al or Au devices). The mechanism is speculated and the different memory behaviors can be tentatively attributed to the different migration processes of the charge carriers under the influence of an electric field. This can offer a new idea for the molecular design of materials with volatile memory.

Regulating the electrical bistable memory characteristics in functional polyimides by varying the spatial position of the electron-donating species

Four novel functional polyimides (PIs) for electrical memory applications, DATP6Cz-DSDA, DATP2Cz-DSDA, DATP6Cz-NTDA, and DATP2Cz-NTDA, were synthesized through condensation polymerization of two diamines, N,N-bis(4-amino)phenyl-6-(9-carbazol)-hexamine (DATP6Cz) and N,N-bis(4-amino)phenyl-2-(9-carbazol)-ethylamine (DATP2Cz), with two dianhydrides, diphenylsulfone-3,3′,4,4′-tetracarboxylic dianhydride (DSDA) and 1,4,5,8-Naphthalenetetracarboxylic dianhydride (NTDA). The ethyl and hexyl spacer were intentionally inserted into the diamines to alter the spatial position of the electron donor in the PIs and then to elucidate the effect on the memory behavior. Experimental results show that DATP6Cz-DSDA and DATP2Cz-DSDA exhibit nonvolatile WORM memory behavior, while DATP6Cz-NTDA and DATP2Cz-NTDA exhibit volatile SRAM and DRAM behavior, respectively. Simulation results indicate much stronger charge-trapping effect of the sulphone moiety in DSDA than that of the carbonyl moiety in NTDA, accounting for the nonvolatile feature of the DSDA-based PI memories and the volatile feature of the NTDA-based PI memories. Meanwhile, spatial position effect was observed in the NTDA-based PIs. The spacer of varied length between carbazole group and diphenyl amino group in DATP6Cz and DATP2Cz, i.e., hexyl vs. ethyl, has significantly altered the spatial position of the electron donor and the charge transportation path in the PIs, resulting in different retention time and corresponding SRAM and DRAM behavior. The present strategy is expected to be applied in material design in future information technology.

The Reach Profiler (REAPER)

Modern DRAM-based systems suffer from significant energy and latency penalties due to conservative DRAM refresh standards. Volatile DRAM cells can retain information across a wide distribution of times ranging from milliseconds to many minutes, but each cell is currently refreshed every 64ms to account for the extreme tail end of the retention time distribution, leading to a high refresh overhead. Due to poor DRAM technology scaling, this problem is expected to get worse in future device generations. Hence, the current approach of refreshing all cells with the worst-case refresh rate must be replaced with a more intelligent design. Many prior works propose reducing the refresh overhead by extending the default refresh interval to a higher value, which we refer to as the target refresh interval, across parts or all of a DRAM chip. These proposals handle the small set of failing cells that cannot retain data throughout the entire extended refresh interval via retention failure mitigation mechanisms (e.g., error correcting codes or bit-repair mechanisms). This set of failing cells is discovered via retention failure profiling, which is currently a brute-force process that writes a set of known data to DRAM, disables refresh and waits for the duration of the target refresh interval, and then checks for retention failures across the DRAM chip. We show that this brute-force approach is too slow and is detrimental to system execution, especially with frequent online profiling. This paper presents reach profiling, a new methodology for retention failure profiling based on the key observation that an overwhelming majority of failing DRAM cells at a target refresh interval fail more reliably at both longer refresh intervals and higher temperatures. Using 368 state-of-the-art LPDDR4 DRAM chips from three major vendors, we conduct a thorough experimental characterization of the complex set of tradeoffs inherent in the profiling process. We identify three key metrics to guide design choices for retention failure profiling and mitigation mechanisms: coverage, false positive rate, and runtime. We propose reach profiling, a new retention failure profiling mechanism whose key idea is to profile failing cells at a longer refresh interval and/or higher temperature relative to the target conditions in order to maximize failure coverage while minimizing the false positive rate and profiling runtime. We thoroughly explore the tradeoffs associated with reach profiling and show that there is significant room for improvement in DRAM retention failure profiling beyond the brute-force approach. We show with experimental data that on average, by profiling at 250ms above the target refresh interval, our first implementation of reach profiling (called REAPER) can attain greater than 99% coverage of failing DRAM cells with less than a 50% false positive rate while running 2.5x faster than the brute-force approach. In addition, our end-to-end evaluations show that REAPER enables significant system performance improvement and DRAM power reduction, outperforming the brute-force approach and enabling high-performance operation at longer refresh intervals that were previously unreasonable to employ due to the high associated profiling overhead.

Write-behind logging

The design of the logging and recovery components of database management systems (DBMSs) has always been influenced by the difference in the performance characteristics of volatile (DRAM) and non-volatile storage devices (HDD/SSDs). The key assumption has been that non-volatile storage is much slower than DRAM and only supports block-oriented read/writes. But the arrival of new non-volatile memory (NVM) storage that is almost as fast as DRAM with fine-grained read/writes invalidates these previous design choices. This paper explores the changes that are required in a DBMS to leverage the unique properties of NVM in systems that still include volatile DRAM. We make the case for a new logging and recovery protocol, called write-behind logging, that enables a DBMS to recover nearly instantaneously from system failures. The key idea is that the DBMS logs what parts of the database have changed rather than how it was changed. Using this method, the DBMS flushes the changes to the database <u>before</u> recording them in the log. Our evaluation shows that this protocol improves a DBMS's transactional throughput by 1.3×, reduces the recovery time by more than two orders of magnitude, and shrinks the storage footprint of the DBMS on NVM by 1.5×. We also demonstrate that our logging protocol is compatible with standard replication schemes.

(Invited) Conductive Bridging RAM (CBRAM): Then, Now, and Tomorrow

Applications of electrochemistry are ubiquitous in modern engineering, but digital computer memory is not typically included in the list. This is because the mainstays of the industry for the past 40 years – volatile DRAM and SRAM and nonvolatile NOR and NAND flash – are all based on the movement and storage of electrons alone, without any accompanying atomic motions. With the advent of nonvolatile Conductive Bridging RAM (CBRAM)*, which operates by the electrically induced making and breaking of atomic-scale conductive filaments inside a solid-state capacitor, electrochemistry has become relevant in the field of digital memory.Here, we present Te-based “subquantum” CBRAM cells as an important step forward in the development of a nonvolatile memory technology with power and performance advantages over flash memory. This new class of CBRAM cells has satisfied technological requirements which CBRAM cells of the past could not meet, such as high-temperature retention, integration into a standard CMOS process with no alterations, full JEDEC qualification, and yields suitable for high-volume manufacturing.The present talk summarizes similarities and differences between subquantum CBRAM cells and CBRAM cells of the past, including their switching mechanisms, materials, electrical characteristics, and commercial applications.For the switching mechanism, a view of the prototypical CBRAM cell as being a tiny electroplating “bath” (typically Cu or Ag) is shown to be poorly suited to subquantum CBRAM cells, whose switching mechanism is suggested to rely on a replacement reaction involving two mobile species (Te and O), neither of which is a metal. A Te filament is formed by this replacement reaction, as inferred from electrical analogies with the Ag- and Cu-based CBRAM cells of the past. Such nonmetal filaments allow subquantum CBRAM cells to reach ON-state conductance levels well below the quantum G0=2e2/h characteristic of a 1-atom filament of a metal (hence the term “subquantum”). New insight into the chemistry of this replacement reaction is deduced here from the influence of the anode stoichiometry.The difference in mechanisms between subquantum CBRAM cells and CBRAM cells of the past drives a difference in materials. For the anode, the necessity of using an amorphous alloy is discussed, and the thermal anneals encountered in standard CMOS processing are shown to place a limitation on which alloys may be used for Te-based cells. Other fundamental and practical requirements for the anode are discussed, as are requirements for the switching layer and anode capping layer.The success of a new memory technology is determined by its acceptance in the market. This depends in part on the qualification, manufacture, and assembly of the new technology being compatible with existing infrastructure. Even with such compatibility, though, the new memory must still offer advantages over the incumbent technologies. Distinguishing features of subquantum CBRAM, as compared to NOR flash, include a low-energy write operation, an ultra-fast write speed, inherently low-voltage operation, a low-power read operation, scalability to CMOS technology nodes below 65nm, and low integration cost.The Internet of Things (IoT) is a market having applications for which these attributes are particularly well-suited. The present talk will discuss select aspects of system and circuit design for the IoT, and will cite examples of IoT-friendly designs which capitalize on the distinguishing features of CBRAM.It is hoped that the present talk is suitable as an introduction to CBRAM, and also as a re-introduction to CBRAM for those familiar with the field as it stood prior to the innovations of the past several years.* Adesto and CBRAM are Trademarks of Adesto Technologies Corp.

Substituent and Charge Transfer Effects on Memory Behavior of the Ambipolar Poly(triphenylamine)s.

A series of poly(triphneylamine)s (CN-PTPA, 2CN-PTPA, 3CN-PTPA, and NO2-PTPA) with pendent acceptors (cyano, dicyanovinyl, tricyanovinyl, and nitro) have been readily synthesized by oxidative coupling polymerization using FeCl3 as oxidant. The tunable memory properties of the ITO/polymer/Al sandwiched memory devices including DRAM, SRAM, and WORM could be achieved by introducing substituent acceptors with different extent of electronic delocalization and electron-withdrawing intensity into the poly(triphenylamine)s. The highly fluorescent CN-PTPA exhibited volatile DRAM memory characteristic due to the large band gap and weak intramolecular charge transfer capability. 2CN-PTPA and 3CN-PTPA showed volatile SRAM memory property with retention time of 5 and 14 min, respectively, depending on electron-withdrawing capability of the acceptors. Furthermore, NO2-PTPA afforded nonvolatile WORM memory behavior attributed to the charge could be trapped into the nonconjugated nitro group even though the dipole moment and electron-withdrawing capability of nitro group were weaker than cyanovinyl groups. Moreover, except NO2-PTPA, all the devices derived from cyano-containing ambipolar polymers including CN-PTPA, 2CN-PTPA, and 3CN-PTPA could be switched to the ON state and exhibited WORM memory behavior in positive unipolar I-V switching. This phenomenon indicated that the Al atoms preferentially interact with poly(triphneylamine)s containing cyano than nitro substituents.

비휘발성 캐시를 사용하는 플래시 메모리 SSD의 데이터베이스 로깅 성능 분석

In a database system, updates on pages that are made by a transaction should be stored in a secondary storage before the commit is complete. Generic secondary storages have volatile DRAM caches to hide long latency for non-volatile media. However, as logs that are only written to the volatile DRAM cache don't ensure durability, logging latency cannot be hidden. Recently, a flash SSD with capacitor-backed DRAM cache was developed to overcome the shortcoming. Storage devices, like those with a non-volatile cache, will increase transaction throughput because transactions can commit as soon as the logs reach the cache. In this paper, we analyzed performance in terms of transaction throughput when the SSD with capacitor-backed DRAM cache was used as log storage. The transaction throughput can be improved over three times, by committing right after storing the logs to the DRAM cache, rather than to a secondary storage device. Also, we showed that it could acquire over 73% of the ideal logging performance with proper tuning.

Map cache management using dual granularity for mobile storage systems

NAND flash memories have been used in many mobile consumer devices as storage media because they are small, fast, shock-resistant, and energy-efficient. However, the flash storage systems based on these flash devices need a special software layer, the FTL, to translate logical addresses from a host system to physical addresses in NAND flash memories. Recently, the flash storage systems in mobile devices tend to employ a page-level mapping scheme as they are required to yield higher access bandwidth. Unlike common SSDs, which often keep the majority of mapping information in fast but volatile DRAM, the flash storage systems in mobile consumer devices keep only a limited subset of mapping information in a small-sized SRAM due to the restrictions in size, cost, and power consumption. For this reason, many cache management schemes proposed for SSDs may not be suitable for the flash storage systems in mobile consumer devices, though most map cache management schemes used in mobile storage are basically designed for SSD. This paper proposes a novel cache management scheme targeting mobile consumer devices. The proposed scheme uses different management granularities in allocating and evacuating cache space. Experimental results show that the proposed scheme improves map cache performance by up to 36% compared to the existing cache management techniques.

Benzothiazole derivatives containing different electron acceptors exhibiting totally different data-storage performances

Two small conjugated molecules BTVCz–NO2 and BTVCz, each incorporating an electron-donating carbazole group and a medium electron-withdrawing benzothiazole group, were both successfully designed and synthesized. Molecule BTVCz–NO2 is an A1–D–A2 structure while BTVCz is a single D–A structure. Both molecules were made into thin films by spin-coating. The two films differentiated over their optical, electrochemical and morphological properties. And the fabricated device with BTVCz–NO2 as an active material showed non-volatile ternary WORM data-storage behavior with its switching threshold voltages at −1.5 V and −2.5 V in tandom when an electrical field was applied, whereas its “counterpart” device with BTVCz as an active material exhibited volatile binary DRAM data-storage behavior with its switching threshold voltage at −1.3 V. Combined with theoretical calculation of each molecule, we conclude that different data-storage behaviors can be achieved by introducing different electron acceptors and that molecule BTVCz–NO2, as an A1–D–A2 structure, is more likely to achieve ternary data-storage performance.