VLIW DSP Processor Research Articles

System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture

System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture

Система комбинируемых специализированных генераторов тестов для нового поколения VLIW DSP процессоров с архитектурой Elcore50

Система комбинируемых специализированных генераторов тестов для нового поколения VLIW DSP процессоров с архитектурой Elcore50

Implementing and Optimizing of Entire System Toolkit of VLIW DSP Processors for Embedded Sensor-Based Systems

VLIW DSPs can largely enhance the Instruction-Level Parallelism, providing the capacity to meet the performance and energy efficiency requirement of sensor-based systems. However, the exploiting of VLIW DSPs in sensor-based domain has imposed a heavy challenge on software toolkit design. In this paper, we present our methods and experiences to develop system toolkit flows for a VLIW DSP, which is designed dedicated to sensor-based systems. Our system toolkit includes compiler, assembler, linker, debugger, and simulator. We have presented our experimental results in the compiler framework by incorporating several state-of-the-art optimization techniques for this VLIW DSP. The results indicate that our framework can largely enhance the performance and energy consumption against the code generated without it.

A Novel Two-Level Instruction Issue Window Based on VLIW Architecture

Instruction compression technique overcomes the drawbacks of traditional VLIW architectures with low density in the instruction cache. However, the separated long instruction word was arranged into two cache line. It comes to be a bottleneck problem for VLIW architecture processor performance because these split long instruction word can not be fetched and issued simultaneously. A novel two-level instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and stores one iteration of the loop body to support software pipeline technique, which improves VLIW DSP processor performance effectively. Proposed machanism was synthesized to evaluate its overall costs, and the performance speedup result for DSP/IMG library bencharks using the cycle accurate simulator are presented.

Operation partitioning for heterogeneous VLIW DSP based on dataflow graph

The Instruction Level Parallelism(ILP) of VLIW DSP processor is acquired through operation partitioning and software pipeline.In the previous research of operation partitioning,people always focus on reducing move operations between clusters,but rarely consider the effect of heterogeneous architecture and some registers that should be placed on reserved cluster.A method based on DataFlow Graph(DFG) for heterogeneous architecture was described to solve this problem.First,the DFG was partitioned into several sub-graphs according to the relations between operations,then the sub-graphs were refined with a heuristic method to meet the requirements of special registers.The experimental results show that this method can make the load of cluster more balanced,and achieve an average of 8% improvement over traditional method.

Guest Editorial

Guest Editorial

LC‐GRFA: global register file assignment with local consciousness for VLIW DSP processors with non‐uniform register files

AbstractEmbedded processors developed within the past few years have employed novel hardware designs to reduce the ever‐growing complexity, power dissipation, and die area. Although using a distributed register file architecture is considered to have less read/write ports than using traditional unified register file structures, it presents challenges in compilation techniques to generate efficient codes for such architectures. This paper presents a novel scheme for register allocation that includes global and local components on a VLIW DSP processor with distributed register files whose port access is highly restricted. In the scheme, an optimization phase performed prior to conventional global/local register allocation, named global/local register file assignment (RFA), is used to minimize various register file communication costs. A heuristic algorithm is proposed for global RFA to make suitable decisions based on local RFA. Experiments were performed by incorporating our schemes on a novel VLIW DSP processor with non‐uniform register files. The results indicate that the compilation based on our proposed approach delivers significant performance improvements, compared with the solution without using our proposed global register allocation scheme. Copyright © 2008 John Wiley & Sons, Ltd.

Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch

High-performance and low-power VLIW DSP processors are increasingly being deployed in mobile devices to process video and multimedia applications. The diverse applications of such systems has led t...

Enabling compiler flow for embedded VLIW DSP processors with distributed register files

High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

AbstractA wide variety of register file architectures—developed for embedded processors—have recently been used with the aim of reducing power dissipation and die size, in contrast with the traditional unified register file structures. This article presents a novel register allocation scheme for a clustered VLIW DSP, which is designed with distinctively banked register files in which port access is highly restricted. Whilst the organization of the register files is designed to decrease power consumption by using fewer port connections, the cluster‐based design makes register access across clusters an additional issue, and the switched‐access nature of the register file demands further investigation into the use of optimizing register assignment as a means of increasing instruction‐level parallelism. We propose a heuristic algorithm, named ping‐pong aware local favorable (PALF) register allocation, to obtain a register allocation that is expected to better utilize irregular register file architectures. The results of experiments performed using a compiler based on the Open Research Compiler (ORC) showed significant performance improvement over the original ORC's approach, which is considered to be an optimized approach for common register file architectures. Copyright © 2007 John Wiley & Sons, Ltd.

A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms

We propose a configurable and scalable architecture targeted for the implementation of advanced wireless communication algorithms based on matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the representation of the algorithm in Matlab/Simulink. The Simulink description is parsed and the algorithm's Dependence Flow Graph is derived, which is scheduled and space---time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable VLIW DSP processors.

Current dynamics-based macro-model for power simulation in a complex VLIW DSP processor

A methodology and a macro-modelling approach are presented for analysing low-level current dynamics at the instruction and program level for a complex VLIW DSP processor core. An instruction-level macro-model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power modelling. For the first time, dynamic power models of algorithms are introduced and verified with real power measurements of a DSP processor core in a VLSI chip. Results from both cryptographic and bubble sort applications show that dynamic power can be modelled with an average error in energy estimation ranging from 0.3% to 9.7%. The instruction-level macro-model of power also supports different clock frequencies and compressed algorithmic traces, important for security aware compilers. In general, the research is important for analysing and modelling the impact of software on power, the design of embedded cryptographic VLSI systems that are safe from power attacks, and for reliable design by detecting the peak current values generated by the software application.