Virtual Reconfigurable Architecture Research Articles

Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

This paper discusses the performance analysis of memetic and genetic algorithms (GA and MA) as the optimising strategy for the design of embedded evolvable hardware. The optimisation algorithm with the fitness evaluation searches for the best configuration to evolve the hardware model. Here, an experimental setup is carried to intrinsically evolve combinational circuits to test the performance of MA and GA. The complete evaluation and evolution is built on a single Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA. A virtual reconfigurable architecture (VRA) with the hardware fitness circuit is modelled as a second reconfigurable layer over the field programmable gate array (FPGA) to configure the target combinational logic. A FPGA soft core processor evaluates the search algorithm and the best solutions are utilised for the hardware evolution. The experimentation results showed that convergence and evolution time of MA was faster compared to GA when the search space was large. Thus, proving MA is a better option for large search space evaluations for evolvable hardware architectures.

Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

This paper discusses the performance analysis of memetic and genetic algorithms (GA and MA) as the optimising strategy for the design of embedded evolvable hardware. The optimisation algorithm with the fitness evaluation searches for the best configuration to evolve the hardware model. Here, an experimental setup is carried to intrinsically evolve combinational circuits to test the performance of MA and GA. The complete evaluation and evolution is built on a single Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA. A virtual reconfigurable architecture (VRA) with the hardware fitness circuit is modelled as a second reconfigurable layer over the field programmable gate array (FPGA) to configure the target combinational logic. A FPGA soft core processor evaluates the search algorithm and the best solutions are utilised for the hardware evolution. The experimentation results showed that convergence and evolution time of MA was faster compared to GA when the search space was large. Thus, proving MA is a better option for large search space evaluations for evolvable hardware architectures.

Application of interactive evolutionary strategy in fault-tolerant system capable of online self-repairing

Evolution mechanism is widely used in triple different-structure modular redundant (D-TMR) fault tolerant system to protect different modules and realise online self-repairing. How to enhance the efficiency and diversity of the generated module by evolution strategy is among the most commonly discussed. The paper puts forward a two-stage mutation evolution strategy (TMES) based on improved virtual reconfigurable architecture platform to evolve combination logical circuit. In order to improve the scalability and increase the diversity of the generated circuit, interactive evolution strategy and heterogeneous degree evaluation are introduced, and then interactive TMES (ITMES) and improved ITMES (IITMES) are presented. The proposed schemes are tested with the evolutions of a 2-bit multiplier, a 3-bit multiplier, and a 3-bit full adder. The obtained results demonstrate that IITMES scheme has better average generation and more circuit type of generated successful individual, and has the potential to strengthen the reliability of the D-TMR system.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture (VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level. The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect (PCI) board with an Xilinx Virtex xcv2000E field programmable gate array (FPGA). To improve the quality of the evolved circuits, the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit. To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning, a self-adaptive mutation rate control (SAMRC) scheme is introduced. In the evolutionary process, the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations. The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function, a 2-bit multiplier, and a 3-bit multiplier. The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort, when compared to the existing evolvable hardware approaches.

Evolutionary design of combinational logic circuits using VRA processor

This paper presents a virtual reconfigurable architecture (VRA)-based evolvable hardware for automatic synthesis of combinational logic circuits. The VRA processor is implemented on a Xilinx FPGA and works through two-stage evolutions: (1) finding a functional circuit, and (2) minimizing the number of gates used. To optimize the algorithm performance in the evolutionary process, a self-adaptive mutation rate control scheme is introduced. The efficiency of the proposed methodology is tested with the evolution of a 3-bit multiplier. The obtained results demonstrate that our approach improves the evolutionary design of electronic circuits in terms of quality of the evolved circuit as well as the computational effort.

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays (FPGAs). The phenotype representation of the proposed evolvable system is based on a two-dimensional function element (FE) network. Compared with the traditional Cartesian genetic programming, the proposed approach includes more connection restrictions in the FE network to reduce genotype length. Another innovative feature of the VRA is that the whole evolvable system, which consists of an evolutionary algorithm unit, a fitness value calculation unit and an FE array unit, can be realised on a single FPGA. On this work, a custom Xilinx Virtex xcv2000E FPGA, which is fitted in the Celoxica RC1000 Peripheral Component Interconnect (PCI) board is utilised as the hardware platform. The main motive of the research is to design a general, flexible evolvable system with powerful computation ability to achieve intrinsic evolution. As examples, the proposed evolvable system is devoted to evolve two real-world applications: a character recogniser and an image operator by using gate level evolution and function level evolution, respectively. The experimental results show that the VRA can bring higher computational ability and more flexibility than traditional approach to intrinsic EHW.